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31. 发明授权

US6118137A Test structure responsive to electrical signals for determining lithographic misalignment of conductors relative to vias 失效
标题翻译：响应于电信号的测试结构，用于确定导体相对于通孔的光刻不对准
公开(公告)号：US6118137A
公开(公告)日：2000-09-12
申请号：US925383
申请日：1997-09-08
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Fred N. Hause
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Fred N. Hause
IPC分类号： H01L23/528 , H01L23/544 , H01L23/58
CPC分类号： H01L22/34 , H01L23/528 , H01L2924/0002
摘要： The present invention advantageously provides a method for determining lithographic misalignment of a conductive element relative to a via. An electrically measured test structure is provided which is designed to have targeted via areas shifted from midlines of corresponding targeted conductor areas. Further, the test structure is designed to have a test pad that electrically communicates with the targeted via areas. Design specifications of the test structure require the midlines of the conductor areas to be offset from the via areas by varying distances. The above-mentioned method involves processing the designed test structure. An electrical signal may then be applied to each of the conductors while it is also being applied to the test pad. The resulting electrical response should be proportional to the distance that a conductor is misaligned from its desired location. Using the electrical responses for all the conductors, it is possible to determine the direction and amount of misalignment.
摘要翻译：本发明有利地提供了一种用于确定导电元件相对于通孔的光刻未对准的方法。提供了一种电测试的测试结构，其被设计成具有从相应的目标导体区域的中线偏移的目标通孔区域。此外，测试结构被设计成具有与目标通孔区域电连通的测试垫。测试结构的设计规范要求导体区域的中线通过不同的距离偏离通孔区域。上述方法涉及处理设计的测试结构。然后可以将电信号施加到每个导体，同时它也被施加到测试垫。所产生的电响应应与导体与其所需位置不对准的距离成正比。使用所有导体的电响应，可以确定未对准的方向和量。

32. 发明授权

US6104063A Multiple spacer formation/removal technique for forming a graded junction 失效
标题翻译：用于形成渐变结的多间隔物形成/去除技术
公开(公告)号：US6104063A
公开(公告)日：2000-08-15
申请号：US942998
申请日：1997-10-02
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/78 , H01L29/76 , H01L27/088
CPC分类号： H01L29/66492 , H01L29/6659 , H01L29/7833 , Y10S257/90
摘要： A transistor and a transistor fabrication method are presented where a sequence of spacers are formed and partially removed upon sidewall surfaces of the gate conductor to produce a graded junction having a relatively smooth doping profile. The spacers include removable and non-removable structures formed on the sidewall surfaces. The adjacent structures have dissimilar etch characteristics compared to each other and compared to the gate conductor. A first dopant (MDD dopant) and a second dopant (source/drain dopant) are implanted into the semiconductor substrate after the respective formation of the removable structure and the non-removable structure. A third dopant (LDD dopant) is implanted into the semiconductor substrate after the removable layer is removed from between the gate conductor and the non-removable structure (spacer). As a result a graded junction is created having higher concentration regions formed outside of lightly concentration regions, relative to the channel area. Such a doping profile provides superior protection against the hot-carrier effect compared to the traditional LDD structure. The smoother the doping profile, the more gradual the voltage drop across the channel/drain junction. A more gradual voltage drop gives rise to a smaller electric field and reduces the hot-carrier effect. Furthermore, the MDD and source/drain implants are performed first, prior to the LDD implant. This allows high-temperature thermal anneals to be performed first, followed by lower temperature anneals second.
摘要翻译：提出了晶体管和晶体管制造方法，其中在栅极导体的侧壁表面上形成并部分地去除间隔物序列，以产生具有相对平滑的掺杂分布的梯度结。间隔件包括形成在侧壁表面上的可移除和不可移除的结构。相邻的结构具有彼此相比的不同的蚀刻特性并且与栅极导体相比较。在可移除结构和不可移除结构的相应形成之后，将第一掺杂剂（MDD掺杂剂）和第二掺杂剂（源极/漏极掺杂剂）注入到半导体衬底中。在可移除层从栅极导体和不可移除结构（间隔物）之间移除之后，将第三掺杂剂（LDD掺杂剂）注入到半导体衬底中。结果，相对于通道面积产生了在轻微浓度区域之外形成的具有较高浓度区域的分级结。与传统的LDD结构相比，这种掺杂分布提供了优于热载体效应的保护。掺杂曲线越平滑，通道/漏极结上的电压降越低。更加缓慢的电压降会导致较小的电场并降低热载流子效应。此外，在LDD植入之前，首先执行MDD和源/漏植入。这允许首先执行高温热退火，其次是较低的温度退火。

33. 发明授权

US6096639A Method of forming a local interconnect by conductive layer patterning 失效
标题翻译：通过导电层图案形成局部互连的方法
公开(公告)号：US6096639A
公开(公告)日：2000-08-01
申请号：US056835
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76895
摘要： A local interconnect (LI) structure is formed by forming a silicide layer in selected regions of a semiconductor structure then depositing an essentially uniform layer of transition or refractory metal overlying the semiconductor structure. The metal local interconnect is deposited without forming in intermediate insulating layer between the silicide and metal layers to define contact openings or vias. In some embodiments, titanium a suitable metal for formation of the local interconnect. Suitable selected regions for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions. The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etchstop layer is desired for the patterning of the metal film, a first optional insulating layer is deposited prior to deposition of the metal film. In one example, the insulating layer is a silicon dioxide (oxide) layer that is typically less than 10 nm in thickness.
摘要翻译：通过在半导体结构的选定区域中形成硅化物层然后沉积覆盖在半导体结构上的基本均匀的过渡或难熔金属层来形成局部互连（LI）结构。在硅化物和金属层之间的中间绝缘层中沉积金属局部互连以限定接触开口或通孔。在一些实施例中，钛是用于形成局部互连的合适金属。用于硅化物层形成的合适的选定区域包括例如硅化源极/漏极（S / D）区域和硅化物栅极接触区域。硅化区域形成均匀的结构，用于电耦合到作为一个或多个半导体器件的部分的下掺杂区域。在需要蚀刻阻挡层用于图案化金属膜的集成电路中，在沉积金属膜之前沉积第一可选绝缘层。在一个示例中，绝缘层是通常小于10nm厚度的二氧化硅（氧化物）层。

34. 发明授权

US6087706A Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls 失效
标题翻译：紧凑的晶体管结构，具有相邻的沟槽隔离和源极/漏极区域，垂直注入沟槽壁
公开(公告)号：US6087706A
公开(公告)日：2000-07-11
申请号：US56834
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/265 , H01L21/762 , H01L21/8234 , H01L29/417 , H01L29/78 , H01L29/00 , H01L29/94
CPC分类号： H01L21/26586 , H01L21/76224 , H01L21/823418 , H01L21/823443 , H01L21/823475 , H01L21/823481 , H01L29/41766 , H01L29/66636 , H01L29/7833
摘要： A semiconductor integrated circuit with a transistor formed within an active area defined by side-walls of a shallow trench isolation region, and method of fabrication thereof, is described. A gate electrode is formed over a portion of the active area and LDD regions formed that are self-aligned to both the gate electrode and the trench side-walls. A dielectric spacer is formed adjacent the gate electrode and extending to the trench side-walls. In this manner, the spacers essentially cover the LDD regions. Source and drain regions are formed that are adjacent the trench side-walls wherein the spacer serves to protect at least a portion of the LDD regions to maintain a spacing of the S/D regions from the gate electrode edge. In this manner an advantageously lowered E.sub.M provided by LDD regions is maintained. In some embodiments of the present invention, S/D regions are formed by implantation through the trench side-walls.
摘要翻译：描述了一种形成在由浅沟槽隔离区域的侧壁限定的有源区域内的晶体管的半导体集成电路及其制造方法。在有源区域的一部分上形成栅电极，形成与栅极电极和沟槽侧壁自对准的LDD区域。形成在栅电极附近并延伸到沟槽侧壁的电介质垫片。以这种方式，间隔件基本上覆盖LDD区域。形成与沟槽侧壁相邻的源极区和漏极区，其中间隔物用于保护LDD区的至少一部分以保持S / D区与栅电极边缘的间隔。以这种方式，维持由LDD区域提供的有利的降低的EM。在本发明的一些实施例中，通过在沟槽侧壁上注入形成S / D区域。

35. 发明授权

US6087705A Trench isolation structure partially bound between a pair of low K dielectric structures 失效
标题翻译：沟槽隔离结构部分地结合在一对低K电介质结构之间
公开(公告)号：US6087705A
公开(公告)日：2000-07-11
申请号：US195592
申请日：1998-11-18
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21/762 , H01L29/00 , H01L23/58
CPC分类号： H01L21/76237
摘要： A process is provided for forming dielectric structures having a relatively low dielectric constant arranged adjacent to the opposed lateral edges of a trench isolation structure. In an embodiment, an opening is etched vertically through a masking layer arranged upon a semiconductor substrate, thereby exposing the surface of the substrate. A patterned photoresist layer is formed upon the masking layer using optical lithography to define the region to be etched. Sidewall spacers made of a low K dielectric material are formed upon the opposed sidewall surfaces of the masking layer within the opening. The sidewall spacers are formed by CVD depositing a dielectric material within the opening and anisotropically etching the dielectric material until only a pre-defined thickness of the material remains upon the masking layer sidewall surfaces. Thereafter, a trench defined between the exposed lateral edges of the sidewall spacers is formed within the substrate. The sidewall spacers permit the lateral width of the trench to be reduced below the minimum lateral dimension definable using lithography. A trench dielectric is formed within the trench such that the upper portion of the dielectric is bound by the sidewall spacers on opposite ends. The resulting trench isolation structure is less likely to experience current leakage when operating an ensuing integrated circuit which employs the isolation structure.
摘要翻译：提供了一种用于形成具有邻近沟槽隔离结构的相对侧边缘布置的相对低的介电常数的介电结构的工艺。在一个实施例中，通过布置在半导体衬底上的掩模层垂直蚀刻开口，从而暴露衬底的表面。使用光刻法在掩模层上形成图案化的光致抗蚀剂层，以限定待蚀刻的区域。由低K电介质材料制成的侧壁隔离物形成在开口内的掩蔽层的相对的侧壁表面上。通过在开口内CVD沉积电介质材料并各向异性地蚀刻电介质材料形成侧壁间隔物，直到材料的预定厚度仅保留在掩模层侧壁表面上为止。此后，在衬底内形成限定在侧壁间隔物的暴露的横向边缘之间的沟槽。侧壁间隔件允许将沟槽的横向宽度减小到使用光刻可定义的最小横向尺寸以下。在沟槽内形成沟槽电介质，使得电介质的上部由相对端上的侧壁间隔件结合。当使用隔离结构的随后集成电路进行操作时，所得到的沟槽隔离结构不太可能经历电流泄漏。

36. 发明授权

US6005285A Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device 有权
标题翻译：用于抑制半导体器件内穿透的氩掺杂外延层
公开(公告)号：US6005285A
公开(公告)日：1999-12-21
申请号：US205321
申请日：1998-12-04
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21/205 , H01L21/336 , H01L29/10 , H01L29/167 , H01L29/32 , H01L29/36
CPC分类号： H01L29/32 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L29/105 , H01L29/1079 , H01L29/167 , H01L29/66537 , H01L29/6659
摘要： A fabrication process and transistor are described in which a transistor having decreased susceptibility to punchthrough and increased resistance to impurity diffusion is formed. One or more argon doped silicon epitaxial layers are formed superjacent a semiconductor substrate. In a preferred dual layer embodiment, a first argon doped silicon epilayer is grown over a substrate, and a second argon doped epilayer, preferably having an argon concentration less than that in the first epilayer, is formed over the first epilayer. A transistor is formed in an active region of a well having a channel laterally bounded by source/drain regions located exclusively in the second epilayer. The lighter argon doping of the second epilayer accommodates current flow in the channel while acting as a barrier to impurity outdiffusion and inhibiting punchthrough. The more heavily doped first epilayer serves primarily as a barrier to outdiffision of impurities from the bulk substrate.
摘要翻译：描述了制造工艺和晶体管，其中形成具有降低的穿透敏感性和增加的杂质扩散阻力的晶体管。在半导体衬底之上形成一个或多个氩掺杂硅外延层。在优选的双层实施例中，在衬底上生长第一氩掺杂硅外延层，并且在第一外延层上形成第二氩掺杂外延层，优选地具有比第一外延层中的氩浓度小的氩浓度。在阱的有源区中形成晶体管，该阱具有由专门位于第二外延层中的源极/漏极区横向限定的沟道。第二外延层的较轻的氩掺杂容纳通道中的电流，同时用作杂质向外扩散的屏障并抑制穿透。掺杂越多的第一外延层主要用作阻挡来自大块基板的杂质的障碍。

37. 发明授权

US5918130A Transistor fabrication employing formation of silicide across source and drain regions prior to formation of the gate conductor 失效
标题翻译：在形成栅极导体之前，使用在源极和漏极区域之间形成硅化物的晶体管制造
公开(公告)号：US5918130A
公开(公告)日：1999-06-29
申请号：US929197
申请日：1997-09-08
申请人： Fred N. Hause , Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Fred N. Hause , Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66621 , H01L29/7834 , Y10S148/10 , Y10S438/951
摘要： The present invention advantageously provides a method for forming a transistor in which silicide contact areas are formed to the junctions during fabrication of the transistor. The silicide contact areas may be formed using a single high temperature anneal since silicide forming near sidewalls of the gate oxide is prevented. In one embodiment, dopants are first forwarded into a lateral region of a silicon-based substrate to form an implant region. Then a silicide layer is formed across the implant region using a high temperature anneal. A sacrificial material is deposited across the silicide layer and the substrate. A contiguous opening is formed vertically through the sacrificial material and the silicide layer, exposing a portion of the substrate. Dopants of the type opposite to the dopants implanted previously are then implanted into the exposed substrate region to form a channel. Thus, the implant region is separated into source and drain regions having a channel interposed between them. Spacers may be formed on opposed sidewall surfaces of the sacrificial material within the opening. A gate oxide is then formed across the exposed region, followed by the formation of a polysilicon gate conductor across the gate oxide. A polycide is formed across the gate conductor before the sacrificial material is removed.
摘要翻译：本发明有利地提供了一种形成晶体管的方法，其中在晶体管的制造期间，其中形成硅化物接触区域到结。可以使用单个高温退火来形成硅化物接触区域，因为防止在栅极氧化物的侧壁附近形成硅化物。在一个实施例中，首先将掺杂剂转移到硅基衬底的横向区域中以形成植入区域。然后使用高温退火在所述注入区域上形成硅化物层。在硅化物层和衬底之间沉积牺牲材料。通过牺牲材料和硅化物层垂直地形成连续的开口，暴露基板的一部分。然后将与先前注入的掺杂剂相反的类型的掺杂剂注入暴露的衬底区域中以形成沟道。因此，注入区被分离成具有介于它们之间的通道的源区和漏区。间隔件可以形成在开口内的牺牲材料的相对的侧壁表面上。然后在暴露区域之间形成栅极氧化物，随后在栅极氧化物上形成多晶硅栅极导体。在除去牺牲材料之前，跨越栅极导体形成多晶硅化物。

38. 发明授权

US5916715A Process of using electrical signals for determining lithographic misalignment of vias relative to electrically active elements 失效
标题翻译：使用电信号确定通孔相对于电活性元件的光刻不对准的过程
公开(公告)号：US5916715A
公开(公告)日：1999-06-29
申请号：US925382
申请日：1997-09-08
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Fred N. Hause
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Fred N. Hause
IPC分类号： G01R31/28 , G03F7/20 , G03F9/00
CPC分类号： G03F7/70633 , G01R31/2805 , G03F7/70658 , G01R31/2813
摘要： The present invention advantageously provides a method for determining lithographic misalignment of a via relative to an electrically active area. An electrically measured test structure is provided which is designed to have targeted via areas shifted from the midline(s) of a targeted active area(s). Further, the test structure is designed to have a test pad(s) that electrically communicates with the targeted active area(s). Design specifications of the test structure require the targeted via areas to be offset from the midline(s) of the active area(s) by varying distances. The above-mentioned method involves processing the designed test structure. An electrical signal may then be applied to conductors coupled to each of the vias while it is also being applied to the test pad. The resulting electrical response should be proportional to the distance that a via is misaligned from its desired location. Using the electrical responses for all the vias, it is possible to determine the direction and amount of misalignment.
摘要翻译：本发明有利地提供了一种用于确定通孔相对于电活动区域的光刻未对准的方法。提供电测量的测试结构，其被设计成具有从目标有源区域的中线偏移的目标通孔区域。此外，测试结构被设计成具有与目标有源区域电连通的测试焊盘。测试结构的设计规范要求目标通孔区域通过变化的距离偏离有效区域的中线。上述方法涉及处理设计的测试结构。然后可以将电信号施加到耦合到每个通孔的导体，同时它也被施加到测试垫。所产生的电响应应与通孔与其所需位置不对准的距离成正比。使用所有通孔的电响应，可以确定未对准的方向和量。

39. 发明授权

US5885887A Method of making an igfet with selectively doped multilevel polysilicon gate 失效
标题翻译：用选择性掺杂多电平多晶硅栅极制造igfet的方法
公开(公告)号：US5885887A
公开(公告)日：1999-03-23
申请号：US847752
申请日：1997-04-21
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/423 , H01L21/38
CPC分类号： H01L29/6659 , H01L21/28114 , H01L21/823842 , H01L29/42376
摘要： A method of making an IGFET with a selectively doped multilevel polysilicon gate that includes upper and lower polysilicon gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a a lower polysilicon layer on the gate insulator, forming a first masking layer over the lower polysilicon layer, etching the lower polysilicon layer through openings in the first masking layer using the first masking layer as an etch mask for a portion of the lower polysilicon layer that forms the lower polysilicon gate level over the active region, removing the first masking layer, forming the upper polysilicon gate level on the lower polysilicon gate level after removing the first masking layer, introducing a dopant into the upper polysilicon gate level without introducing the dopant into the substrate, diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level, and forming a source and drain in the active region. Advantageously, the lower polysilicon gate level has both an accurately defined length to provide the desired channel length and a well-controlled doping concentration to provide the desired threshold voltage.
摘要翻译：公开了一种制造具有选择性掺杂多电平多晶硅栅极的IGFET的方法，其包括上和下多晶硅栅极电平。该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上形成下部多晶硅层，在下部多晶硅层上形成第一掩蔽层，通过下部多晶硅层的开口蚀刻下部多晶硅层所述第一掩模层使用所述第一掩模层作为用于在所述有源区上形成所述下多晶硅栅极电平的所述下多晶硅层的一部分的蚀刻掩模，去除所述第一掩模层，在所述下多晶硅栅极上形成所述上多晶硅栅极电平在去除第一掩模层之后，将掺杂剂引入上多晶硅栅极级，而不将掺杂剂引入衬底中，将掺杂剂从上多晶硅栅极级扩散到下多晶硅栅极电平，并在活性层中形成源极和漏极地区。有利地，下多晶硅栅极电平具有精确限定的长度以提供期望的沟道长度和良好控制的掺杂浓度以提供期望的阈值电压。

40. 发明授权

US5882973A Method for forming an integrated circuit having transistors of dissimilarly graded junction profiles 失效
标题翻译：用于形成具有不同分级结型材的晶体管的集成电路的方法
公开(公告)号：US5882973A
公开(公告)日：1999-03-16
申请号：US789549
申请日：1997-01-27
申请人： Mark I. Gardner , Fred N. Hause , H. Jim. Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim. Fulford, Jr.
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823468 , H01L21/823864
摘要： An integrated circuit is provided having a plurality of transistors either NMOS transistors, or PMOS transistors, or both NMOS and PMOS transistors. The transistors are formed having dissimilarly sized spacers. The spacers can be made larger in lateral areas on transistors designated as lower performing transistors than smaller spacers used on transistors which are higher performing. The dissimilarly sized spacers produce correspondingly sized lightly doped drain (LDD) areas. Accordingly, the present integrated circuit includes on a single monolithic substrate both high and low performance transistors based upon formation of dissimilarly sized spacers at sidewall surfaces of select transistor gate conductors.
摘要翻译：提供了具有多个晶体管的集成电路，NMOS晶体管或PMOS晶体管，或NMOS晶体管和PMOS晶体管。晶体管形成为具有不同尺寸的间隔物。在表现较高的晶体管上使用的间隔物可以比被称为低性能晶体管的晶体管的横向区域更大。不同尺寸的间隔件产生相应尺寸的轻掺杂漏极（LDD）区域。因此，本集成电路基于在选择晶体管栅极导体的侧壁表面处形成不同尺寸的间隔物，在单个单片基板上包括高性能和低性能晶体管。

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