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1. 发明授权

US6121631A Test structure to determine the effect of LDD length upon transistor performance 失效
标题翻译：测试结构，以确定LDD长度对晶体管性能的影响
公开(公告)号：US6121631A
公开(公告)日：2000-09-19
申请号：US267444
申请日：1999-03-12
申请人： Mark I Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L23/544 , H01L29/78 , H01L23/58 , H01L27/088 , H01L31/119
CPC分类号： H01L29/6659 , H01L22/34 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , Y10S257/90
摘要： The present invention advantageously provides a method for forming a test structure for determining how LDD length of a transistor affects transistor characteristics. In one embodiment, a first polysilicon gate conductor is provided which is laterally spaced from a second polysilicon gate conductor. The gate conductors are each disposed upon a gate oxide lying above a silicon-based substrate. An LDD implant is forwarded into exposed regions of the substrate to form LDD areas within the substrate adjacent to the gate conductors. A first spacer material is then formed upon sidewall surfaces of both gate conductors to a first pre-defined thickness. Source/drain regions are formed exclusively within the substrate a spaced distance from the first gate conductor, the spaced distance being dictated by the first pre-defined thickness. A second spacer material is formed laterally adjacent to the first spacer material to a second pre-defined distance. Source/drain regions are then formed within the substrate a spaced distance from the second gate conductor, the spaced distance being dictated by the second predefined thickness. The resulting transistors have a mutual source/drain region between them. More transistors may also be fabricated in a similar manner.
摘要翻译：本发明有利地提供了一种用于形成用于确定晶体管的LDD长度如何影响晶体管特性的测试结构的方法。在一个实施例中，提供了与第二多晶硅栅极导体横向间隔开的第一多晶硅栅极导体。栅极导体各自设置在位于硅基衬底之上的栅极氧化物上。将LDD植入物转移到衬底的暴露区域中，以在邻近栅极导体的衬底内形成LDD区域。然后将第一间隔物材料形成在两个栅极导体的侧壁表面上至第一预定义的厚度。源极/漏极区域仅在衬底内形成与第一栅极导体间隔开的距离，间隔距离由第一预定义厚度决定。第二间隔物材料横向地邻近第一间隔物材料形成为第二预定距离。源极/漏极区域然后在衬底内形成与第二栅极导体间隔开的距离，间隔距离由第二预定厚度决定。所得的晶体管在它们之间具有相互的源极/漏极区域。也可以以类似的方式制造更多的晶体管。

2. 发明授权

US5970354A Poly recessed fabrication method for defining high performance MOSFETS 失效
标题翻译：用于定义高性能MOSFET的多凹陷制造方法
公开(公告)号：US5970354A
公开(公告)日：1999-10-19
申请号：US987117
申请日：1997-12-08
申请人： Fred N. Hause , Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Fred N. Hause , Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/66583 , H01L21/28123
摘要： A method for forming a gate conductor by using a masking layer above a polysilicon layer to define the length of a gate is presented. The length of the gate may be adjusted by the use of spacers. The method includes forming a plurality of layers including a dielectric layer, a polysilicon layer and a masking layer. An opening is preferably formed in the masking layer, the opening defining the location of the gate conductor. The width of the opening may be narrowed by the use of spacers. A portion of the polysilicon layer defined by the opening is implanted with an n-type impurity. An oxide layer is formed over the implanted portion of the polysilicon layer. The polysilicon layer is etched such that a gate conductor is formed underneath the oxide layer. LDD areas and source/drain areas are subsequently formed adjacent to the gate conductor.
摘要翻译：提出了一种通过使用多晶硅层上面的掩模层来形成栅极导体的方法，以限定栅极的长度。栅极的长度可以通过使用间隔物来调节。该方法包括形成包括电介质层，多晶硅层和掩模层的多个层。优选地，在掩模层中形成开口，该开口限定栅极导体的位置。开口的宽度可以通过使用间隔物变窄。由开口限定的多晶硅层的一部分注入n型杂质。在多晶硅层的注入部分上形成氧化物层。蚀刻多晶硅层，使得在氧化物层下方形成栅极导体。随后在栅极导体附近形成LDD区域和源极/漏极区域。

3. 发明授权

US5946579A Stacked mask integration technique for advanced CMOS transistor formation 失效
标题翻译：叠层掩模集成技术，用于先进的CMOS晶体管形成
公开(公告)号：US5946579A
公开(公告)日：1999-08-31
申请号：US987277
申请日：1997-12-09
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Fred N. Hause
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Fred N. Hause
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/336
CPC分类号： H01L29/66583 , H01L21/28052 , H01L21/28123 , H01L21/32137
摘要： A method for forming a gate conductor by using a masking layer above a polysilicon layer to define the length of a gate is presented. The length of the gate may be adjusted by the use of spacers. The method includes forming a plurality of layers including a dielectric layer, a polysilicon layer and a masking layer. An opening is preferably formed in the masking layer, the opening defining the location of the gate conductor. The width of the opening may be narrowed by the use of spacers. A portion of the polysilicon layer defined by the opening is implanted with an n-type impurity. A silicide layer is formed upon the upper surface of the exposed polysilicon layer. An oxide layer is formed over the silicide layer. The polysilicon layer is etched such that a gate conductor is formed underneath the oxide layer. LDD areas and source/drain areas are subsequently formed adjacent to the gate conductor.
摘要翻译：提出了一种通过使用多晶硅层上面的掩模层来形成栅极导体的方法，以限定栅极的长度。栅极的长度可以通过使用间隔物来调节。该方法包括形成包括电介质层，多晶硅层和掩模层的多个层。优选地，在掩模层中形成开口，该开口限定栅极导体的位置。开口的宽度可以通过使用间隔物变窄。由开口限定的多晶硅层的一部分注入n型杂质。在暴露的多晶硅层的上表面上形成硅化物层。在硅化物层上形成氧化物层。蚀刻多晶硅层，使得在氧化物层下方形成栅极导体。随后在栅极导体附近形成LDD区域和源极/漏极区域。

4. 发明授权

US6072192A Test structure responsive to electrical signals for determining lithographic misalignment of vias relative to electrically active elements 失效
标题翻译：响应于电信号的测试结构，用于确定通孔相对于电活性元件的光刻不对准
公开(公告)号：US6072192A
公开(公告)日：2000-06-06
申请号：US252365
申请日：1999-02-18
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Fred N. Hause
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Fred N. Hause
IPC分类号： G01R31/28 , G03F7/20 , H01L23/58 , H01L23/544
CPC分类号： G03F7/70633 , G01R31/2805 , G03F7/70658 , G01R31/2813
摘要： The present invention advantageously provides a method for determining lithographic misalignment of a via relative to an electrically active area. An electrically measured test structure is provided which is designed to have targeted via areas shifted from the midline(s) of a targeted active area(s). Further, the test structure is designed to have a test pad(s) that electrically communicates with the targeted active area(s). Design specifications of the test structure require the targeted via areas to be offset from the midline(s) of the active area(s) by varying distances. The above-mentioned method involves processing the designed test structure. An electrical signal may then be applied to conductors coupled to each of the vias while it is also being applied to the test pad. The resulting electrical response should be proportional to the distance that a via is misaligned from its desired location. Using the electrical responses for all the vias, it is possible to determine the direction and amount of misalignment.
摘要翻译：本发明有利地提供了一种用于确定通孔相对于电活动区域的光刻未对准的方法。提供电测量的测试结构，其被设计成具有从目标有源区域的中线偏移的目标通孔区域。此外，测试结构被设计成具有与目标有源区域电连通的测试焊盘。测试结构的设计规范要求目标通孔区域通过变化的距离偏离有效区域的中线。上述方法涉及处理设计的测试结构。然后可以将电信号施加到耦合到每个通孔的导体，同时它也被施加到测试垫。所产生的电响应应与通孔与其所需位置不对准的距离成正比。使用所有通孔的电响应，可以确定未对准的方向和量。

5. 发明授权

US5918134A Method of reducing transistor channel length with oxidation inhibiting spacers 失效
标题翻译：用氧化抑制间隔物减少晶体管沟道长度的方法
公开(公告)号：US5918134A
公开(公告)日：1999-06-29
申请号：US666922
申请日：1996-06-19
申请人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L29/78 , H01L21/266
CPC分类号： H01L29/66583 , H01L29/66492 , H01L29/66613 , H01L29/7834 , H01L29/7836
摘要： A method of fabricating a transistor. A dielectric layer is formed on an upper surface of a semiconductor substrate. A photoresist layer is then deposited on a dielectric layer and patterned with a photolithography exposure device to expose a region of the dielectric layer having a lateral dimension approximately equal to the minimum feature size resolvable by the photolithography exposure device. The exposed region of the dielectric layer is then removed to form a trench in the dielectric layer having opposed dielectric sidewalls and to expose a channel region of the semiconductor substrate having a lateral dimension approximately equal to the minimum feature size. First and second spacer structures are then formed on the respective dielectric sidewalls. The spacer structures shadow peripheral portions of the exposed channel region. A channel dielectric is then formed between the first and second spacer structures. An outer surface of the spacer structure is then removed to expose peripheral portions of the channel region. A first concentration of a first impurity is then introduced into the peripheral portions of the semiconductor substrate and the channel dielectric is thereafter removed. A gate dielectric is then formed on the semiconductor substrate and a conductive gate structure, such as polysilicon, is formed over the gate dielectric.
摘要翻译：一种制造晶体管的方法。在半导体衬底的上表面上形成介电层。然后将光致抗蚀剂层沉积在电介质层上并用光刻曝光装置进行图案化，以暴露电介质层的区域，该区域的横向尺寸近似等于由光刻曝光装置可分辨的最小特征尺寸。然后去除电介质层的暴露区域，以在具有相对的电介质侧壁的电介质层中形成沟槽，并暴露半导体衬底的沟道区域，其横向尺寸近似等于最小特征尺寸。然后在相应的电介质侧壁上形成第一和第二间隔物结构。间隔结构遮挡了暴露的通道区域的外围部分。然后在第一和第二间隔结构之间形成沟道电介质。然后移除间隔结构的外表面以暴露通道区域的外围部分。然后将第一杂质的第一浓度引入半导体衬底的周边部分，然后除去沟道电介质。然后在半导体衬底上形成栅极电介质，并且在栅极电介质上形成诸如多晶硅的导电栅极结构。

6. 发明授权

US5895955A MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch 失效
标题翻译： MOS晶体管采用可移除的双层蚀刻停止件，以保护植入区域免受侧壁间隔物过蚀刻
公开(公告)号：US5895955A
公开(公告)日：1999-04-20
申请号：US781451
申请日：1997-01-10
申请人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L29/78 , H01L29/72
CPC分类号： H01L29/6659 , H01L29/7833 , H01L29/665
摘要： A transistor and transistor fabrication method are presented where a sequence of layers are formed and either entirely or partially removed upon sidewall surfaces of a gate conductor. The formation and removal of layers produces a series of laterally spaced surfaces to which various implants can be aligned. Those implants, placed in succession produce a highly graded junction having a relatively smooth doping profile. The multilayer spacer structure comprises a polysilicon spacer interposed between a grown oxide and an etch stop. The polysilicon spacer is formed by an anisotropic etch, and the pre-existing etch stop prevents the anisotropic etch from damaging the source/drain and gate conductor regions beneath the etch stop. Further, the etch stop allows removal of the overlying oxide as well as the entire polysilicon during times when the multi-layer spacer is entirely removed. Removal of the various layers does not damage the underlying substrate due to the presence of the etch stop. The etch stop preferably comprises a nitride layer overlying an oxide layer, wherein the oxide layer can either be deposited or grown.
摘要翻译：提出了一种晶体管和晶体管制造方法，其中形成一系列层，并且在栅极导体的侧壁表面上完全或部分地去除层。层的形成和去除产生一系列横向间隔开的表面，各种植入物可以对齐。连续放置的那些植入物产生具有相对平滑的掺杂分布的高度梯度的结。多层间隔结构包括插入生长的氧化物和蚀刻停止层之间的多晶硅间隔物。通过各向异性蚀刻形成多晶硅间隔物，并且预先存在的蚀刻停止物防止各向异性蚀刻损坏蚀刻停止点下面的源极/漏极和栅极导体区域。此外，在完全去除多层间隔物的时间期间，蚀刻停止允许去除上覆氧化物以及整个多晶硅。由于存在蚀刻停止，各层的去除不会损坏下面的衬底。蚀刻停止件优选地包括覆盖氧化物层的氮化物层，其中氧化物层可以沉积或生长。

7. 发明授权

US06184566B2 Method and structure for isolating semiconductor devices after transistor formation 失效
标题翻译：在晶体管形成之后隔离半导体器件的方法和结构
公开(公告)号：US06184566B2
公开(公告)日：2001-02-06
申请号：US09150776
申请日：1998-09-10
申请人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L2176
CPC分类号： H01L21/823418 , H01L21/76237 , H01L21/823425 , H01L21/823481 , Y10S257/90
摘要： A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes laterally displaced source/drain regions and channel regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. The first and second transistors have a common source/drain region. An isolation trench is formed through the common source/drain region and the trench is filled with a trench dielectric material such that the common source/drain region is divided into electrically isolated first and second source/drain regions whereby the first transistor is electrically isolated from the second transistor.
摘要翻译：一种用于隔离半导体器件的方法，包括提供半导体衬底。半导体衬底包括横向移位的源极/漏极区域和沟道区域。第一和第二横向位移的MOS晶体管部分地形成在半导体衬底内。第一和第二晶体管具有公共源极/漏极区域。通过公共源极/漏极区形成隔离沟槽，并且沟槽填充有沟槽电介质材料，使得公共源极/漏极区域被分成电隔离的第一和第二源极/漏极区域，由此第一晶体管与第二晶体管。

8. 发明授权

US6117760A Method of making a high density interconnect formation 失效
标题翻译：制造高密度互连结构的方法
公开(公告)号：US6117760A
公开(公告)日：2000-09-12
申请号：US968682
申请日：1997-11-12
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Fred N. Hause
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Fred N. Hause
IPC分类号： H01L21/768 , H01L23/528 , H01L21/4763
CPC分类号： H01L21/76885 , H01L21/76838 , H01L23/5283 , H01L2924/0002
摘要： A technique is provided for forming interconnects laterally spaced from each other across a semiconductor topography by a deposited dielectric spacer layer. The lateral distance between each interconnect is advantageously dictated by the thickness of the spacer layer rather than by the minimum feature size of a lithographically patterned masking layer. In an embodiment, a first and second conductive interconnects are formed a spaced distance apart upon a semiconductor topography. The first and second interconnects are defined using optical lithography and an etch technique. A dielectric layer is CVD deposited across the exposed surfaces of the first and second interconnects and of the semiconductor topography. The CVD deposition conditions are controlled so as to form a relatively thin spacers laterally adjacent the sidewalls of the interconnects. A conductive material is then deposited across into a trench arranged between the first and second interconnects, and CMP polished such that the upper surface of the conductive material is at an elevational level proximate that of the surfaces of the interconnects. A third interconnect is thereby formed within the trench laterally adjacent the first and second interconnects.
摘要翻译：提供了一种技术，用于通过沉积的介电隔离层在半导体形貌上形成横向间隔开的互连。每个互连之间的横向距离有利地由隔离层的厚度而不是光刻图案化掩模层的最小特征尺寸决定。在一个实施例中，第一和第二导电互连在半导体形貌上分开形成间隔距离。第一和第二互连使用光刻和蚀刻技术来定义。介电层是跨越第一和第二互连的暴露表面和半导体形貌的CVD沉积的。控制CVD沉积条件以形成横向邻近互连侧壁的较薄的间隔件。然后将导电材料沉积到布置在第一和第二互连之间的沟槽中，并且CMP抛光，使得导电材料的上表面处于靠近互连表面的上表面。因此，在沟槽内形成第三互连件，横向地邻近第一和第二互连。

9. 发明授权

US6107129A Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance 失效
标题翻译：具有多个LDD和/或源极/漏极注入步骤以增强电路性能的集成电路
公开(公告)号：US6107129A
公开(公告)日：2000-08-22
申请号：US38511
申请日：1998-03-11
申请人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L29/78 , H01L29/72
CPC分类号： H01L29/6659 , H01L29/7833 , H01L29/7835
摘要： An integrated circuit is formed whereby MOS transistor junctions are produced which enhance the overall speed of the integrated circuit. The transistor junctions include multiple implants into the lightly doped drain (LDD) areas of the junction, the source/drain areas of the junction or both the LDD and source/drain areas. The first implant of the multiple implants serves to condition the implant area so that the second and subsequent implants are accurately placed with relatively high concentrations closely below the substrate surface. The resulting junction is therefore one which has relatively high drive strength, low contact resitivity, low source-to-drain parasitic resistance, and relatively low junction capacitance.
摘要翻译：形成集成电路，由此产生提高集成电路总体速度的MOS晶体管结。晶体管结包括多个注入到结点的轻掺杂漏极（LDD）区域，结点的源极/漏极区域以及LDD和源极/漏极区域两者。多个植入物的第一植入物用于调节植入区域，使得第二和随后的植入物以相对高的浓度精确地放置在基底表面附近。因此，所得到的结是具有相对高的驱动强度，低接触电阻率，低的源到漏寄生电阻和相对低的结电容的结。

10. 发明授权

US5837572A CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein 失效
标题翻译： CMOS集成电路通过使用可移除间隔物在不对称PMOS结之间产生不对称的NMOS结形成，用于优化植入其中的掺杂剂的热扩散率
公开(公告)号：US5837572A
公开(公告)日：1998-11-17
申请号：US781461
申请日：1997-01-10
申请人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L21/8238 , H01L21/82
CPC分类号： H01L21/823814 , H01L29/66659 , H01L29/7835
摘要： An integrated circuit is provided having both NMOS transistors and PMOS transistors. The NMOS transistor junction regions are preferably formed before the PMOS transistor junction regions with pre-defined anneal temperatures applied after select implant steps. Both the NMOS and PMOS transistor junction are graded such that the drain areas include a relatively large LDD implant area and the source junctions do not. Whatever LDD area pre-existing in the source implanted with a higher concentration source/drain or MDD implant. The ensuing integrated circuit is therefore a CMOS circuit having asymmetrical transistor junctions and carefully controlled implant and anneal sequences. The asymmetrical junctions are retained, or at least optimized, by controlling the anneal temperatures such that diffusivity distances of n-type implants are relatively similar to p-type implants. Diffusivity is controlled by regulating the post-implant anneal temperatures of p-type implants lesser than previous n-type implants.
摘要翻译：提供具有NMOS晶体管和PMOS晶体管的集成电路。 NMOS晶体管结区优选地在具有预定义的退火温度的PMOS晶体管结区之后形成在选择的注入步骤之后。 NMOS和PMOS晶体管结都被分级，使得漏极区域包括相对较大的LDD注入区域，并且源极结不包括。无论在植入较高浓度源/漏或MDD植入物的源中预先存在LDD区域。因此，随后的集成电路是具有不对称晶体管结和仔细控制的注入和退火序列的CMOS电路。通过控制退火温度使得n型植入物的扩散距离相对于p型植入物保持或至少优化不对称结。通过调节比以前的n型植入物少的p型植入物的植入后退火温度来控制扩散性。

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