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31. 发明授权

US6057063A Phase shifted mask design system, phase shifted mask and VLSI circuit devices manufactured therewith 失效
标题翻译：相移掩模设计系统，相移掩模和用其制造的VLSI电路器件
公开(公告)号：US6057063A
公开(公告)日：2000-05-02
申请号：US824700
申请日：1997-04-14
申请人： Lars W. Liebmann , Ioana C. Graur , Young O. Kim , Mark A. Lavin , Alfred K. Wong
发明人： Lars W. Liebmann , Ioana C. Graur , Young O. Kim , Mark A. Lavin , Alfred K. Wong
IPC分类号： G03F1/00 , G06F17/50 , G03F9/00
CPC分类号： G06F17/5068 , G03F1/26
摘要： A process for creating and verifying a design of phase-shifted masks utilizing at least one phase shift region employing a computer-aided design system. A chip design is provided. A phase-shift mask design capable of producing the chip design is created. Features in a design of the phase-shifted mask that require phase shifting are located. Uncolored phase regions are created on opposite sides of the features. Proper phase termination of the phase regions is ensured based upon space constraints of a phase-shifted mask technique utilized. Phases are determined for the phase regions. Whether coloring errors and un-phase-shiftable design features exist is determined. Mask process specific overlaps and expansions are applied to the mask design to prepare designed data levels for mask manufacture. A residual phase edge image removal design is derived.
摘要翻译：利用采用计算机辅助设计系统的至少一个相移区域来创建和验证相移掩模的设计的过程。提供芯片设计。产生了能够产生芯片设计的相移掩模设计。定位需要相移的相移掩模设计中的特征。未着色的相位区域在特征的相对侧上创建。基于所采用的相移掩模技术的空间限制，确保相位区域的正确相位终止。确定相位区域的相位。是否存在着色误差和不相移设计特征。掩模过程特定的重叠和扩展被应用于掩模设计以准备用于掩模制造的设计的数据级。导出残留相边缘图像去除设计。

32. 发明授权

US08219943B2 Physical design system and method 有权
标题翻译：物理设计系统及方法
公开(公告)号：US08219943B2
公开(公告)日：2012-07-10
申请号：US12425603
申请日：2009-04-17
申请人： John M Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
发明人： John M Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
IPC分类号： G06F17/50 , G06F19/00 , G03F1/00 , G21K5/00
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
摘要翻译：一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。布局单元接收表示网格和字形格式的部分的电路描述。检查单元检查设计的网格和字形部分。精心设计单元从检查的设计生成目标布局。数据准备单元准备掩模制作的目标布局。模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

33. 发明申请

US20090204930A1 IPHYSICAL DESIGN SYSTEM AND METHOD 有权
标题翻译：物理设计系统与方法
公开(公告)号：US20090204930A1
公开(公告)日：2009-08-13
申请号：US12425603
申请日：2009-04-17
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
摘要翻译：一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。布局单元接收表示网格和字形格式的部分的电路描述。检查单元检查设计的网格和字形部分。精心设计单元从检查的设计生成目标布局。数据准备单元准备掩模制作的目标布局。模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

34. 发明授权

US5671152A Efficient generation of negative fill shapes for chips and packages 失效
标题翻译：为芯片和封装提供有效的负填充形状
公开(公告)号：US5671152A
公开(公告)日：1997-09-23
申请号：US444471
申请日：1995-05-19
申请人： Mark A. Lavin , Lars W. Liebmann
发明人： Mark A. Lavin , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： An efficient method for modifying a chip or package design allows for the creation of small shapes without excessive expansion of design data. A computer program takes a physical design, represented in a computer data file, and generates a modified version of the design in which fill holes have been added. Subsequently, when the modified design is processed, the resulting semiconductor chip or package will contain physical images of the added fill holes, with the effect of making local pattern density more uniform and hence reducing process-induced variations in feature size and shape.
摘要翻译：修改芯片或封装设计的有效方法允许创建小形状而不会过度扩展设计数据。计算机程序采用计算机数据文件中的物理设计，并生成其中添加了填充孔的设计的修改版本。随后，当改进的设计被处理时，所得到的半导体芯片或封装将包含所添加的填充孔的物理图像，具有使局部图案密度更均匀并因此减少特征尺寸和形状的工艺引起的变化的效果。

35. 发明授权

US08516403B2 Multiple patterning layout decomposition for ease of conflict removal 有权
标题翻译：多重图案化布局分解，便于冲突删除
公开(公告)号：US08516403B2
公开(公告)日：2013-08-20
申请号：US13223844
申请日：2011-09-01
申请人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
发明人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A mechanism is provided for multiple patterning lithography with conflict removal aware coloring. The mechanism makes multiple patterning coloring aware of the conflict removal overhead. The coloring solution explicitly considers ease of conflict removal as one of the coloring objectives. The mechanism pre-computes how much shapes can move in each direction. The mechanism generates a conflict graph where nodes represent shapes in the layout and edges represent conflicts between shapes. The mechanism assigns weights to edges based on available spatial slack between conflicting features. The mechanism then uses the weights to guide multiple patterning coloring. The mechanism prioritizes conflicting features with higher weights to be assigned different colors.
摘要翻译：提供了一种用于具有冲突消除意识着色的多重图案化光刻的机构。该机制使得多个图案化着色意识到冲突移除开销。着色解决方案明确地将冲突移除的容易性作为着色目标之一。该机制预先计算出每个方向上可以移动多少形状。该机制生成一个冲突图，其中节点表示布局中的形状，边缘表示形状之间的冲突。该机制基于冲突特征之间的可用空间松弛来为边缘分配权重。该机构然后使用重量来引导多个图案化着色。该机制优先处理具有较高权重的冲突特征，以分配不同的颜色。

36. 发明授权

US08225255B2 Placement and optimization of process dummy cells 有权
标题翻译：过程虚拟细胞的放置和优化
公开(公告)号：US08225255B2
公开(公告)日：2012-07-17
申请号：US12124472
申请日：2008-05-21
申请人： Xu Ouyang , Geng Han , Lars W. Liebmann
发明人： Xu Ouyang , Geng Han , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G11C29/24 , G06F2217/12 , G11C5/02 , H01L27/0203 , H01L27/105 , Y02P90/265
摘要： A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.
摘要翻译：与存储器阵列的内部存储单元相关地布置处理虚设单元的方法包括：（a）计算存储器阵列的初始处理性能参数; （b）改变电连接到内部单元的层的虚拟单元布局配置; （c）为内部存储单元和改变的布局配置处理虚拟单元应用光刻模拟和屈服模型; 和（d）重复步骤（b）和（c），直到产率最大化。可以进行检查，以确保有足够的空间进行更改，并且对相邻电路没有明显的不利影响。过程性能参数可以是产量或内部存储器单元的处理窗口。

37. 发明授权

US08103983B2 Electrically-driven optical proximity correction to compensate for non-optical effects 有权
标题翻译：电动光学接近校正补偿非光学效果
公开(公告)号：US08103983B2
公开(公告)日：2012-01-24
申请号：US12269477
申请日：2008-11-12
申请人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/10
摘要： A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip.
摘要翻译：改进了用于集成电路的掩模设计的轮廓，以补偿由非光学效应（例如应力，阱接近度，快速热退火或间隔物厚度）引起的系统变化。提取使用掩模设计制造的模拟集成电路芯片的电气特性，并将其与设计规范进行比较，并调整轮廓的一个或多个边缘以减少系统变化，直到电气特性在规格范围内。特定的电特性优选地取决于由掩模制成的层：多晶硅的导通电流; 接触阻力; 金属电阻和电容; 当前活跃; 和通孔阻力。对于系统阈值电压变化，调整轮廓以根据芯片的标称阈值电压下的轮廓电流和栅极长度的预先计算的曲线来匹配对应于导通电流值的栅极长度。

38. 发明申请

US20100122231A1 ELECTRICALLY-DRIVEN OPTICAL PROXIMITY CORRECTION TO COMPENSATE FOR NON-OPTICAL EFFECTS 有权
标题翻译：电动驱动光学近似校正补偿非光学效应
公开(公告)号：US20100122231A1
公开(公告)日：2010-05-13
申请号：US12269477
申请日：2008-11-12
申请人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/10
摘要： A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip.
摘要翻译：改进了用于集成电路的掩模设计的轮廓，以补偿由非光学效应（例如应力，阱接近度，快速热退火或间隔物厚度）引起的系统变化。提取使用掩模设计制造的模拟集成电路芯片的电气特性，并将其与设计规范进行比较，并调整轮廓的一个或多个边缘以减少系统变化，直到电气特性在规格范围内。特定的电特性优选地取决于由掩模制成的层：多晶硅的导通电流; 接触阻力; 金属电阻和电容; 当前活跃; 和通孔阻力。对于系统阈值电压变化，调整轮廓以根据芯片的标称阈值电压下的轮廓电流和栅极长度的预先计算的曲线来匹配对应于导通电流值的栅极长度。

39. 发明授权

US06338922B1 Optimized alternating phase shifted mask design 失效
标题翻译：优化交替相移掩模设计
公开(公告)号：US06338922B1
公开(公告)日：2002-01-15
申请号：US09566885
申请日：2000-05-08
申请人： Lars W. Liebmann , Alfred K. Wong
发明人： Lars W. Liebmann , Alfred K. Wong
IPC分类号： G03F900
CPC分类号： G03F7/70425 , G03F1/30
摘要： A method for reducing lens aberrations sensitivity and proximity effects of alternating phase shifted masks is described. The critical features of a chip design layout are first identified. Multiple, narrow phase regions and auxiliary phase transitions, which provide additional opaque features, are then formed alongside the critical features such that a grating pattern of substantially uniform pitch is printed. Together with a complementary trim mask, the circuit pattern so delineated has reduced sensitivity to lens aberrations and proximity effects.
摘要翻译：描述了用于减少交替相移掩模的透镜像差灵敏度和邻近效应的方法。首先确定了芯片设计布局的关键特征。然后，在临界特征旁边形成提供附加的不透明特征的多个窄相位区域和辅助相位转变，使得印刷基本均匀的间距的光栅图案。与互补的修剪掩模一起，如此描绘的电路图案降低了对透镜像差和邻近效应的敏感性。

40. 发明授权

US5936738A Focus monitor for alternating phase shifted masks 有权
标题翻译：交替相移掩模的聚焦监视器
公开(公告)号：US5936738A
公开(公告)日：1999-08-10
申请号：US127741
申请日：1998-08-03
申请人： Lars W. Liebmann , Richard A. Ferguson
发明人： Lars W. Liebmann , Richard A. Ferguson
IPC分类号： G01B11/02 , G03F1/26 , G03F7/20 , G01B11/00
CPC分类号： G03F7/70641 , G01B11/026 , G03F7/70283 , G03F1/26
摘要： A focus monitor for establishing best focus of a lithographic system in semiconductor wafers. The focus monitor has a phase region having a first phase and a slot disposed within the phase region having a gap size indicative of a defocus level of the lithographic system.
摘要翻译：用于建立半导体晶片中光刻系统最佳焦点的聚焦监视器。聚焦监视器具有相位区域，该相位区域具有设置在相位区域内的具有指示光刻系统的散焦水平的间隙尺寸的第一相位和狭槽。

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