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31. 发明申请

US20070204447A1 Intralevel decoupling capacitor, method of manufacture and testing circuit of the same 有权
标题翻译：内部去耦电容器，制造和测试电路的方法
公开(公告)号：US20070204447A1
公开(公告)日：2007-09-06
申请号：US11707060
申请日：2007-02-16
申请人： Kerry Bernstein , John Bracchitta , William Cote , Tak Ning , Wilbur Pricer
发明人： Kerry Bernstein , John Bracchitta , William Cote , Tak Ning , Wilbur Pricer
IPC分类号： H01G7/00
CPC分类号： H01G4/1272 , H01G4/35 , H01L22/14 , H01L22/22 , H01L23/5223 , H01L23/642 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.
摘要翻译：为半导体器件提供去耦电容器，并且可以包括在单个互连平面中在第一低介电绝缘体的表面上形成至少两个交叉指示图案的第一低介电绝缘体层和低电阻导体。可以在两个图案之间提供高介电常数材料。还提供了用于测试多个这些电容器的电路，其包括充电监视电路，耦合电路和控制电路。

32. 发明申请

US20060208760A1 Low leakage monotonic CMOS logic 有权
公开(公告)号：US20060208760A1
公开(公告)日：2006-09-21
申请号：US11407176
申请日：2006-04-19
申请人： Kerry Bernstein , Norman Rohrer
发明人： Kerry Bernstein , Norman Rohrer
IPC分类号： H03K19/0175
CPC分类号： G06F17/505 , H03K19/0016 , H03K19/0948
摘要： A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic stages having a predominantly high input state or having a predominantly low input state; wherein the logic stages having the predominantly high input state, comprise one or more thin gate dielectric and high threshold voltage PFETs with respect to a reference PFET and one or more thick gate dielectric and low threshold voltage NFETs with respect to a reference NFET; and wherein the logic stages having the predominantly low input state, comprise one or more thick gate dielectric and low threshold voltage PFETs with respect to the reference PFET and one or more thin gate dielectric and high threshold voltage NFETs with respect to the reference NFET.

33. 发明申请

US20060026457A1 Error correcting logic system 有权
标题翻译：错误校正逻辑系统
公开(公告)号：US20060026457A1
公开(公告)日：2006-02-02
申请号：US10710641
申请日：2004-07-27
申请人： Kerry Bernstein , Philip Emma , John Fifield , Paul Kartschoke , William Klaasen , Norman Rohrer
发明人： Kerry Bernstein , Philip Emma , John Fifield , Paul Kartschoke , William Klaasen , Norman Rohrer
IPC分类号： G06F11/00
CPC分类号： H03K19/007
摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.
摘要翻译：本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。该系统适用于动态或静态逻辑系统。该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。

34. 发明授权

US06882015B2 Intralevel decoupling capacitor, method of manufacture and testing circuit of the same 失效
公开(公告)号：US06882015B2
公开(公告)日：2005-04-19
申请号：US10660755
申请日：2003-09-12
申请人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
发明人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
IPC分类号： H01L21/02 , H01L27/08 , H01L29/76
CPC分类号： H01G4/1272 , H01G4/35 , H01L22/14 , H01L22/22 , H01L23/5223 , H01L23/642 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

35. 发明授权

US06670683B2 Composite transistor having a slew-rate control 失效
公开(公告)号：US06670683B2
公开(公告)日：2003-12-30
申请号：US09754156
申请日：2001-01-04
申请人： Kerry Bernstein , Anthony Correale, Jr. , Terence Blackwell Hook , Douglas Willard Stout
发明人： Kerry Bernstein , Anthony Correale, Jr. , Terence Blackwell Hook , Douglas Willard Stout
IPC分类号： H01L2976
CPC分类号： H01L29/1041
摘要： A metal oxide semiconductor transistor having a slew-rate control is disclosed. The transistor having a slew-rate control includes an elongated diffusion area and an elongated gate overlying the diffusion area. The elongated diffusion area has at least two diffusion regions, each having a threshold voltage that is different from each other. The elongated gate has a gate contact at only one side of the elongated diffusion area.

36. 发明授权

US06523159B2 Method for adding decoupling capacitance during integrated circuit design 有权
标题翻译：在集成电路设计期间添加去耦电容的方法
公开(公告)号：US06523159B2
公开(公告)日：2003-02-18
申请号：US09761464
申请日：2001-01-16
申请人： Kerry Bernstein , John M. Cohn , Jose L. P. Neves
发明人： Kerry Bernstein , John M. Cohn , Jose L. P. Neves
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method and a related program storage product for adding decoupling capacitance in an integrated circuit during the floor planning stage of the integrated circuit design. The invention overlay a power grid on the floor plan and then divides the power grid into regions or macros. For each region or macro, a support decoupling capacitance value required to support a voltage of the power grid and a native capacitance value are determined. Based on those values, a required decoupling capacitance value along with its decoupling capacitance area is determined. The design is then alternated based on the decoupling capacitance area.
摘要翻译：一种用于在集成电路设计的平面布置阶段期间在集成电路中添加去耦电容的方法和相关程序存储产品。本发明在平面图上覆盖电网，然后将电网划分为区域或宏。对于每个区域或宏，确定支持电网电压所需的支持去耦电容值和固有电容值。基于这些值，确定所需的去耦电容值及其去耦电容面积。然后基于去耦电容面积交替设计。

37. 发明授权

US06453431B1 System technique for detecting soft errors in statically coupled CMOS logic 失效
标题翻译：用于检测静态耦合CMOS逻辑中的软错误的系统技术
公开(公告)号：US06453431B1
公开(公告)日：2002-09-17
申请号：US09346509
申请日：1999-07-01
申请人： Kerry Bernstein , Andres Bryant , William A. Klaasen , Wilbur David Pricer
发明人： Kerry Bernstein , Andres Bryant , William A. Klaasen , Wilbur David Pricer
IPC分类号： G06K504
CPC分类号： G11C5/005 , G06F11/00
摘要： Circuit for detecting error transients in logic circuits due to atomic events or other non-recurring noise sources includes a first circuit coupled to a data line for sensing a first signal on the data line at a first point in time (T1) and a second circuit coupled to the data line for sensing the first signal on the data line at a second point in time (T2) such that a time difference between T1 and T2 is small enough so that the first signal is still present on the data line in the absence of a perturbation event and such that the time difference between T1 and T2 is large enough so that any such perturbation event is resolved. A compare circuit coupled to the first and second circuits compares the sensing of the first signal by the first and second circuits, and generates an error signal in response to a non-compare.
摘要翻译：用于检测由于原子事件或其他非循环噪声源引起的逻辑电路中的错误瞬变的电路包括耦合到数据线的第一电路，用于感测在第一时间点（T1）的数据线上的第一信号，以及第二电路耦合到数据线，用于在第二时间点（T2）感测数据线上的第一信号，使得T1和T2之间的时间差足够小，使得第一信号在不存在的情况下仍然存在于数据线上的扰动事件，并且使得T1和T2之间的时间差足够大，使得任何这样的扰动事件被解决。耦合到第一和第二电路的比较电路比较第一和第二电路对第一信号的感测，并且响应于非比较而产生误差信号。

38. 发明授权

US6091273A Voltage limiting circuit for fuse technology 失效
标题翻译：保险丝技术限压电路
公开(公告)号：US6091273A
公开(公告)日：2000-07-18
申请号：US914857
申请日：1997-08-19
申请人： Kerry Bernstein , Daniel Charles Edelstein , William Alan Klaasen , Wilbur David Pricer
发明人： Kerry Bernstein , Daniel Charles Edelstein , William Alan Klaasen , Wilbur David Pricer
IPC分类号： G11C17/18 , H03K17/687 , H03L5/00
CPC分类号： H03K17/6872 , G11C17/18
摘要： A voltage limiting circuit for fuse technology. The voltage limiting circuit is coupled to the two terminals. The voltage limiting circuit is responsive to a fuse blow through a low impedance sensing circuit, and then minimizes the voltage across the fuse gap that is created by the fuse blow. Thus, the invention prevents dendritic growth and corrosion in copper or similar types of fuses.
摘要翻译：一种用于保险丝技术的限压电路。电压限制电路耦合到两个端子。电压限制电路响应于通过低阻抗感测电路的保险丝熔断，然后使由保险丝熔断产生的熔丝间隙上的电压最小化。因此，本发明防止了铜或类似类型的保险丝中的树枝状生长和腐蚀。

39. 发明授权

US4742487A Inhibit and transfer circuitry for memory cell being read from multiple ports 失效
标题翻译：用于从多个端口读取的存储器单元的禁止和传送电路
公开(公告)号：US4742487A
公开(公告)日：1988-05-03
申请号：US852465
申请日：1986-04-15
申请人： Kerry Bernstein
发明人： Kerry Bernstein
IPC分类号： G11C11/41 , G11C8/16 , G11C11/401 , G11C11/419 , G11C7/00
CPC分类号： G11C8/16
摘要： An inhibit and transfer circuit for a memory system having multiple read ports. Bit lines are precharged. In a reading operation, the precharging is disconnected at the same time that the bit lines are selectively connected to one or more sense latches, associated with multiple reading ports. Feedback paths in the sense latches are disconnected during the reading. The selection of the sense latches to which the bit lines are coupled is determined by a comparison of multiple addressing signals.
摘要翻译：一种用于具有多个读端口的存储器系统的抑制和传输电路。位线预充电。在读取操作中，在与多个读取端口相关联的一个或多个感测锁存器选择性地连接位线的同时，预充电被断开。在读取期间，感测锁存器中的反馈路径被断开。通过比较多个寻址信号来确定位线耦合到的读出锁存器的选择。

40. 发明授权

US4577292A Support circuitry for multi-port systems 失效
标题翻译：支持多端口系统的电路
公开(公告)号：US4577292A
公开(公告)日：1986-03-18
申请号：US499729
申请日：1983-05-31
申请人： Kerry Bernstein
发明人： Kerry Bernstein
IPC分类号： G11C11/417 , G11C7/00 , G11C8/16 , G11C8/18 , G11C8/20 , G11C11/41 , H01L27/10 , G11C13/00
CPC分类号： G11C8/16 , G11C7/00 , G11C8/18 , G11C8/20
摘要： The present invention is especially directed towards an improved support circuitry for a memory array which utilizes support circuitry in a memory array such that, when an address compare occurs, selected one of the array word decoders are disabled to prevent a multiple read, and selected higher order read heads are disabled and the output data of the highest order bit lines is transferred onto all of the lower order bit lines having the same address as the uninhibited word decoder.
摘要翻译：本发明特别涉及用于存储器阵列的改进的支持电路，该支持电路利用存储器阵列中的支持电路，使得当发生地址比较时，所选择的一个阵列字解码器被禁止以防止多次读取并选择更高顺序读取头被禁用，并且最高位位线的输出数据被传送到具有与非禁止字解码器相同的地址的所有低位位线上。

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