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1. 发明授权

US06523159B2 Method for adding decoupling capacitance during integrated circuit design 有权
标题翻译：在集成电路设计期间添加去耦电容的方法
公开(公告)号：US06523159B2
公开(公告)日：2003-02-18
申请号：US09761464
申请日：2001-01-16
申请人： Kerry Bernstein , John M. Cohn , Jose L. P. Neves
发明人： Kerry Bernstein , John M. Cohn , Jose L. P. Neves
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method and a related program storage product for adding decoupling capacitance in an integrated circuit during the floor planning stage of the integrated circuit design. The invention overlay a power grid on the floor plan and then divides the power grid into regions or macros. For each region or macro, a support decoupling capacitance value required to support a voltage of the power grid and a native capacitance value are determined. Based on those values, a required decoupling capacitance value along with its decoupling capacitance area is determined. The design is then alternated based on the decoupling capacitance area.
摘要翻译：一种用于在集成电路设计的平面布置阶段期间在集成电路中添加去耦电容的方法和相关程序存储产品。本发明在平面图上覆盖电网，然后将电网划分为区域或宏。对于每个区域或宏，确定支持电网电压所需的支持去耦电容值和固有电容值。基于这些值，确定所需的去耦电容值及其去耦电容面积。然后基于去耦电容面积交替设计。

2. 发明授权

US06490708B2 Method of integrated circuit design by selection of noise tolerant gates 失效
公开(公告)号：US06490708B2
公开(公告)日：2002-12-03
申请号：US09812211
申请日：2001-03-19
申请人： John M. Cohn , Scott W. Gould , Peter A. Habitz , Jose L. P. Neves , William F. Smith , Larry Wissel , Paul S. Zuchowski
发明人： John M. Cohn , Scott W. Gould , Peter A. Habitz , Jose L. P. Neves , William F. Smith , Larry Wissel , Paul S. Zuchowski
IPC分类号： G06E1750
CPC分类号： G06F17/505
摘要： A method of integrated circuit design using the selective replacement of increasingly noise tolerant cells is disclosed. The method involves compiling a library comprising a plurality of design element cells, sorting the library into groups of functionally-equivalent cells, and ordering the cells in each group from one extreme to the other extreme value of a featured parameter for which the integrated circuit is to be tested. Each one of the cells in the library have a known value of another parameter so that the substitution of a library cell for an original cell or another library cell does not affect the overall integrated circuit value for that known parameter. A substitution can thus be made with the knowledge that additional problems involving the known parameter are not being created. If a test of the integrated circuit discovers a problem in a particular cell's performance with regard to the featured parameter the appropriate library group is accessed and the failing cell is replaced with the first unused cell in the group. The process is repeated until the integrated circuit passes a performance test.

3. 发明授权

US08640075B2 Early design cycle optimzation 失效
标题翻译：早期设计周期优化
公开(公告)号：US08640075B2
公开(公告)日：2014-01-28
申请号：US13486177
申请日：2012-06-01
申请人： Charles Jay Alpert , Robert M. Averill, III , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
发明人： Charles Jay Alpert , Robert M. Averill, III , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
摘要翻译：一些示例性实施例包括用于设计集成电路的计算机实现的方法。计算机实现的方法包括接收集成电路的分层网络设计，其中分层设计包括耦合在一起的多个组件。计算机实现的方法包括基于包括缺失断言，一个或多个缺失锁存器，源驱动程序中的至少一个的问题，检测组件数量的组件具有故障定时和不完整定时中的至少一个输入源电压大于源极限极限阈值，以及具有大于漏极极限极限阈值的输入接收器的接收器。计算机实现的方法包括使用独立于问题的不同组件替换组件，并且基于不同的组件测试组件数量的其他组件。

4. 发明申请

US20130326450A1 EARLY DESIGN CYCLE OPTIMZATION 失效
标题翻译：早期设计周期优化
公开(公告)号：US20130326450A1
公开(公告)日：2013-12-05
申请号：US13486177
申请日：2012-06-01
申请人： Charles Jay Alpert , Robert M. Averill , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
发明人： Charles Jay Alpert , Robert M. Averill , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
摘要翻译：一些示例性实施例包括用于设计集成电路的计算机实现的方法。计算机实现的方法包括接收集成电路的分层网络设计，其中分层设计包括耦合在一起的多个组件。计算机实现的方法包括基于包括缺失断言，一个或多个缺失锁存器，源驱动程序中的至少一个的问题，检测组件数量的组件具有故障定时和不完整定时中的至少一个输入源电压大于源极限极限阈值，以及具有大于漏极极限极限阈值的输入接收器的接收器。计算机实现的方法包括使用独立于问题的不同组件替换组件，并且基于不同的组件测试组件数量的其他组件。

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