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31. 发明申请

US20060043590A1 MAINTAINING UNIFORM CMP HARD MASK THICKNESS 有权
标题翻译：维持均匀的CMP硬掩模厚度
公开(公告)号：US20060043590A1
公开(公告)日：2006-03-02
申请号：US10711145
申请日：2004-08-27
申请人： Steven Shyng-Tsong Chen , Kaushik Kumar , Stephen Greco , Shom Ponoth , Terry Spooner , David Rath , Wei-Tsu Tseng
发明人： Steven Shyng-Tsong Chen , Kaushik Kumar , Stephen Greco , Shom Ponoth , Terry Spooner , David Rath , Wei-Tsu Tseng
IPC分类号： H01L21/4763 , H01L23/48 , H01L23/52 , H01L29/40 , H01L21/31 , H01L21/469
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/76832 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.
摘要翻译：化学机械抛光（CMP）步骤用于去除覆盖在具有填充有导电材料的沟槽的低k或超低k层间介质层（ILD）层上的过剩导电材料（例如Cu），用于镶嵌互连结构。使用反应离子蚀刻（RIE）或气体簇离子束（GCIB）方法去除位于硬掩模顶部的衬垫的一部分。使用湿蚀刻步骤去除覆盖在ILD上的硬掩模的氧化物部分，随后是最后的上覆Cu CMP（CMP）步骤，其将突出的Cu图案切掉并落在SiCOH硬掩模上。以这种方式，用于去除过量的导电材料的工艺基本上不影响覆盖层间电介质层的硬掩模的部分。

32. 发明授权

US06975032B2 Copper recess process with application to selective capping and electroless plating 有权
公开(公告)号：US06975032B2
公开(公告)日：2005-12-13
申请号：US10319967
申请日：2002-12-16
申请人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

33. 发明申请

US20100210098A1 SELF-ALIGNED CONTACT 有权
标题翻译：自对准联系人
公开(公告)号：US20100210098A1
公开(公告)日：2010-08-19
申请号：US12372174
申请日：2009-02-17
申请人： Johnathan E. Faltermeier , Stephan Grunow , Kangguo Cheng , Kevin Petrarca , Kaushik Kumar , Lawrence A. Clevenger , Shom Ponoth , Vidhya Ramachandran
发明人： Johnathan E. Faltermeier , Stephan Grunow , Kangguo Cheng , Kevin Petrarca , Kaushik Kumar , Lawrence A. Clevenger , Shom Ponoth , Vidhya Ramachandran
IPC分类号： H01L21/283
CPC分类号： H01L21/76897 , H01L21/0337 , H01L21/31144 , H01L21/76829
摘要： A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, filling the divots with an initial fill material, depositing a masking material on the dielectric over the gate stacks, and selectively etching the fill material to form contact vias. The fill material may be a self-assembly material such as a multi-block copolymer in which the blocks self organize vertically within the divots, so that a selective etch of the block material will remove the vertically organized blocks from the divot, but leave at least one block over the gate regions. In another embodiment, the fill material may be a metal, and the masking material may be a parylene based polymer.
摘要翻译：一种形成用于半导体器件的触点的方法，所述方法包括在多个栅极叠层之间沉积层间电介质（ILD），其中层间电介质层内的阴影由栅极堆叠之间的空间限定，填充具有初始填充材料的图案，在栅极堆叠上的电介质上沉积掩模材料，并且选择性地蚀刻填充材料以形成接触孔。填充材料可以是自组装材料，例如多嵌段共聚物，其中嵌段自由地在密封区内垂直组织，使得嵌段材料的选择性蚀刻将从竖纹中去除垂直组织的块，而是离开在门区域上至少有一个块。在另一个实施方案中，填充材料可以是金属，掩蔽材料可以是聚对二甲苯基聚合物。

34. 发明申请

US20080042174A1 FIELD EFFECT TRANSISTORS (FETS) WITH INVERTED SOURCE/DRAIN METALLIC CONTACTS, AND METHOD OF FABRICATING SAME 有权
标题翻译：具有反相源/漏电金属接触的场效应晶体管（FET）及其制造方法
公开(公告)号：US20080042174A1
公开(公告)日：2008-02-21
申请号：US11923075
申请日：2007-10-24
申请人： Michael Belyansky , Dureseti Chidambarrao , Lawrence Clevenger , Kaushik Kumar , Carl Radens
发明人： Michael Belyansky , Dureseti Chidambarrao , Lawrence Clevenger , Kaushik Kumar , Carl Radens
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76804 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.
摘要翻译：本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。优选地，倒置的源极/漏极金属接触件的下部具有约0.03毫米2至约3.15微米的横截面积，并且这样的反相源 /漏极金属触点与FET的栅电极间隔约0.001μm至约5μm的距离。

35. 发明申请

US20060264036A1 Line level air gaps 审中-公开
标题翻译：线路气隙
公开(公告)号：US20060264036A1
公开(公告)日：2006-11-23
申请号：US11491816
申请日：2006-07-24
申请人： Shyng-Tsong Chen , Stefanie Chiras , Matthew Colburn , Tomothy Dalton , Jeffrey Hedrick , Elbert Huang , Kaushik Kumar , Michael Lane , Kelly Malone , Chandrasekhar Narayan , Satyanarayana Nitta , Sampath Purushothaman , Robert Rosenberg , Christy Tyberg , Roy Yu
发明人： Shyng-Tsong Chen , Stefanie Chiras , Matthew Colburn , Tomothy Dalton , Jeffrey Hedrick , Elbert Huang , Kaushik Kumar , Michael Lane , Kelly Malone , Chandrasekhar Narayan , Satyanarayana Nitta , Sampath Purushothaman , Robert Rosenberg , Christy Tyberg , Roy Yu
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.
摘要翻译：在多电平微电子集成电路中，空气包括永久线路电介质，超低K材料通过电介质。在通过清洁热分解除去牺牲材料并通过IC结构中的孔隙率辅助副产物扩散后，将空气供应到线路电平。任选地，空气也包括在通孔级电介质中的孔隙中。通过将空气结合到本发明产生的程度，使层内和层间介电值最小化。

36. 发明申请

US20060124993A1 SIDEWALL SEMICONDUCTOR TRANSISTORS 有权
标题翻译：端子半导体晶体管
公开(公告)号：US20060124993A1
公开(公告)日：2006-06-15
申请号：US10905041
申请日：2004-12-13
申请人： Huilong Zhu , Lawrence Clevenger , Omer Dokumaci , Kaushik Kumar , Carl Radens , Dureseti Chidambarrao
发明人： Huilong Zhu , Lawrence Clevenger , Omer Dokumaci , Kaushik Kumar , Carl Radens , Dureseti Chidambarrao
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/1083 , H01L29/66795
摘要： A novel transistor structure and method for fabricating the same. The transistor structure comprises (a) a substrate and (b) a semiconductor region, a gate dielectric region, and a gate region on the substrate, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate region, wherein the semiconductor region is electrically insulated from the gate region by the gate dielectric region, wherein the semiconductor region comprises a channel region and first and second source/drain regions, wherein the channel region is sandwiched between the first and second source/drain regions, wherein the first and second source/drain regions are aligned with the gate region, wherein the channel region and the gate dielectric region (i) share an interface surface which is essentially perpendicular to a top surface of the substrate, and (ii) do not share any interface surface that is essentially parallel to a top surface of the substrate.
摘要翻译：一种新颖的晶体管结构及其制造方法。晶体管结构包括（a）衬底和（b）衬底上的半导体区域，栅极介电区域和栅极区域，其中栅极电介质区域夹在半导体区域和栅极区域之间，其中半导体区域通过所述栅极电介质区域与所述栅极区域电绝缘，其中所述半导体区域包括沟道区域和第一和第二源极/漏极区域，其中所述沟道区域夹在所述第一和第二源极/漏极区域之间，其中所述第一和/ 第二源极/漏极区域与栅极区域对准，其中沟道区域和栅极电介质区域（i）共享基本上垂直于衬底顶表面的界面，以及（ii）不共享任何界面表面其基本上平行于衬底的顶表面。

37. 发明申请

US20060118961A1 Dual damascene integration of ultra low dielectric constant porous materials 有权
公开(公告)号：US20060118961A1
公开(公告)日：2006-06-08
申请号：US11341338
申请日：2006-01-26
申请人： Kaushik Kumar , Kelly Malone , Christy Tyberg
发明人： Kaushik Kumar , Kelly Malone , Christy Tyberg
IPC分类号： H01L23/48
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , H01L21/76807 , H01L21/76831 , H01L21/76835 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

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