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1. 发明授权

US07614083B2 Process control methods and apparatus for intrusion detection, protection and network hardening 有权
标题翻译：用于入侵检测，保护和网络硬化的过程控制方法和设备
公开(公告)号：US07614083B2
公开(公告)日：2009-11-03
申请号：US11078082
申请日：2005-03-11
申请人： Bharat Khuti , Clayton Coleman , David Rath , Ernest Rakaczky , Jim Leslie , Juan Peralta , George Simpson
发明人： Bharat Khuti , Clayton Coleman , David Rath , Ernest Rakaczky , Jim Leslie , Juan Peralta , George Simpson
IPC分类号： G06F11/00
CPC分类号： H04L63/1416 , H04L63/02 , H04L63/0209 , H04L63/105 , H04L63/14 , H04L63/20 , H04L67/12
摘要： The invention provides an improved network and methods of operation thereof for use in or with process control systems, computer-based manufacturing or production control systems, environmental control systems, industrial control system, and the like (collectively, “control systems”). Those networks utilize a unique combination of firewalls, intrusion detection systems, intrusion protection devices and/or other devices for hardening (e.g., security against hacking, intrusion or other mischievous conduct) and/or intrusion detection. The networks and methods have application, by way of example, in plants, sites and other facilities in which networks that support control systems interface with corporate, business or other networks.
摘要翻译：本发明提供一种改进的网络及其操作方法，用于过程控制系统，基于计算机的制造或生产控制系统，环境控制系统，工业控制系统等（统称为“控制系统”）。这些网络使用防火墙，入侵检测系统，入侵保护设备和/或其他设备（例如，防止入侵，入侵或其他恶作剧行为的安全性）和/或入侵检测的独特组合。网络和方法通过示例的方式应用于工厂，站点和其他支持控制系统的网络与企业，企业或其他网络接口的设施。

2. 发明申请

US20050158985A1 Copper recess process with application to selective capping and electroless plating 有权
标题翻译：铜凹槽工艺，适用于选择性封盖和无电镀
公开(公告)号：US20050158985A1
公开(公告)日：2005-07-21
申请号：US11058783
申请日：2005-02-16
申请人： Shyng-Tsong Chen , Timothy Dalton , Kenneth Davis , Chao-Kun Hu , Fen Jamin , Steffen Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael Lofaro , Sandra Malhotra , Chandrasekhar Narayan , David Rath , Judith Rubino , Katherine Saenger , Andrew Simon , Sean Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy Dalton , Kenneth Davis , Chao-Kun Hu , Fen Jamin , Steffen Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael Lofaro , Sandra Malhotra , Chandrasekhar Narayan , David Rath , Judith Rubino , Katherine Saenger , Andrew Simon , Sean Smith , Wei-tsu Tseng
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44 , H01L21/4763 , H01L21/48
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.
摘要翻译：公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

3. 发明申请

US20050081884A1 Semiconductor device cleaning employing heterogeneous nucleation for controlled cavitation 有权
标题翻译：采用异质成核的半导体器件清洗用于受控空化
公开(公告)号：US20050081884A1
公开(公告)日：2005-04-21
申请号：US10685684
申请日：2003-10-15
申请人： Ravikumar Ramachandran , David Rath
发明人： Ravikumar Ramachandran , David Rath
IPC分类号： B08B3/12 , C11D1/02 , C11D1/38 , C11D7/24 , C11D7/26 , C11D11/00 , C25F1/00 , H01L21/00 , H01L21/306
CPC分类号： H01L21/02052 , B08B3/12 , C11D1/02 , C11D1/38 , C11D7/241 , C11D7/261 , C11D11/0047 , H01L21/67057 , Y10S134/902
摘要： The present invention provides a method cleaning of semiconductor devices through heterogeneous nucleation of cavitation bubbles. Heterogeneous nucleation is performed by applying sonic energy to a cleaning solution and a phase material in order to remove unwanted particles from semiconductor devices. A surfactant may be added to the phase material and the cleaning solution.
摘要翻译：本发明提供了通过空化气泡的异质成核来清洗半导体器件的方法。通过将声能施加到清洁溶液和相材料以便从半导体器件中去除不需要的颗粒来进行非均匀成核。可以向相材料和清洁溶液中加入表面活性剂。

4. 发明授权

US07761923B2 Process control methods and apparatus for intrusion detection, protection and network hardening 有权
标题翻译：用于入侵检测，保护和网络硬化的过程控制方法和设备
公开(公告)号：US07761923B2
公开(公告)日：2010-07-20
申请号：US11069465
申请日：2005-03-01
申请人： Bharat Khuti , Clayton Coleman , David Rath , Ernest Rakaczky , Jim Leslie , Juan Peralta , George Simpson
发明人： Bharat Khuti , Clayton Coleman , David Rath , Ernest Rakaczky , Jim Leslie , Juan Peralta , George Simpson
IPC分类号： G06F9/00 , G06F11/00 , G06F7/04
CPC分类号： H04L63/1416 , H04L63/02 , H04L63/0209 , H04L63/105 , H04L63/14 , H04L63/20 , H04L67/12
摘要： The invention provides an improved network and methods of operation thereof for use in or with process control systems, computer-based manufacturing or production control systems, environmental control systems, industrial control system, and the like (collectively, “control systems”). Those networks utilize a unique combination of firewalls, intrusion detection systems, intrusion protection devices and/or other devices for hardening (e.g., security against hacking, intrusion or other mischievous conduct) and/or intrusion detection. The networks and methods have application, by way of example, in plants, sites and other facilities in which networks that support control systems interface with corporate, business or other networks.
摘要翻译：本发明提供一种改进的网络及其操作方法，用于过程控制系统，基于计算机的制造或生产控制系统，环境控制系统，工业控制系统等（统称为“控制系统”）。这些网络使用防火墙，入侵检测系统，入侵保护设备和/或其他设备（例如，防止入侵，入侵或其他恶作剧行为的安全性）和/或入侵检测的独特组合。网络和方法通过示例的方式应用于工厂，站点和其他支持控制系统的网络与企业，企业或其他网络接口的设施。

5. 发明申请

US20070117377A1 Conductor-dielectric structure and method for fabricating 审中-公开
标题翻译：导体 - 电介质结构及其制造方法
公开(公告)号：US20070117377A1
公开(公告)日：2007-05-24
申请号：US11286093
申请日：2005-11-23
申请人： Chih-Chao Yang , Shom Ponoth , David Rath , Keith Wong
发明人： Chih-Chao Yang , Shom Ponoth , David Rath , Keith Wong
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76865 , H01L21/76868 , H01L21/76873 , H01L2221/1089
摘要： A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.
摘要翻译：通过提供包括其中具有图案化特征的电介质层的结构来制造导体 - 电介质互连结构; 在所述图案化特征中的所述电介质层上沉积电镀种子层; 在通孔的电镀种子层上沉积牺牲种子层; 通过反向电镀减少牺牲种子层的厚度; 以及在所述图案化特征中的所述牺牲种子层上镀覆导电金属。还提供了其中具有通孔的电介质层; 图案化特征中的电介质层上的电镀种子层; 以及位于图案化特征中的不连续牺牲种子层。

6. 发明申请

US20060089000A1 Material and process for etched structure filling and planarizing 审中-公开
标题翻译：蚀刻结构填充和平面化的材料和工艺
公开(公告)号：US20060089000A1
公开(公告)日：2006-04-27
申请号：US10973683
申请日：2004-10-26
申请人： Ronald Della Guardia , Ranee Kwong , Wenjie Li , Qinghuang Lin , Dirk Pfeiffer , David Rath
发明人： Ronald Della Guardia , Ranee Kwong , Wenjie Li , Qinghuang Lin , Dirk Pfeiffer , David Rath
IPC分类号： H01L21/461 , C09K13/00 , H01L21/302
CPC分类号： H01L21/76808 , C09K13/08 , H01L21/31144
摘要： In the back end of integrated circuits employing low-k interlevel dielectrics, etched structures are filled with a planarizing material comprising a cyclic olefin polymer and solvent; the next pattern to be etched is defined in a photosensitive layer above the planarizing layer; the pattern is etched in the dielectric and the planarizing material is stripped in a wet process that does not damage the interlevel dielectric.
摘要翻译：在采用低k层间电介质的集成电路的后端，用包含环烯烃聚合物和溶剂的平面化材料填充蚀刻结构; 待蚀刻的下一个图案被限定在平坦化层上方的感光层中; 在电介质中蚀刻图案，并且在不损坏层间电介质的湿法中剥离平面化材料。

7. 发明申请

US20060053491A1 Process control methods and apparatus for intrusion detection, protection and network hardening 有权
公开(公告)号：US20060053491A1
公开(公告)日：2006-03-09
申请号：US11078082
申请日：2005-03-11
申请人： Bharat Khuti , Clayton Coleman , David Rath , Ernest Rakaczky , Jim Leslie , Juan Peralta , George Simpson
发明人： Bharat Khuti , Clayton Coleman , David Rath , Ernest Rakaczky , Jim Leslie , Juan Peralta , George Simpson
IPC分类号： G06F12/14 , G06F15/173
CPC分类号： H04L63/1416 , H04L63/02 , H04L63/0209 , H04L63/105 , H04L63/14 , H04L63/20 , H04L67/12
摘要： The invention provides an improved network and methods of operation thereof for use in or with process control systems, computer-based manufacturing or production control systems, environmental control systems, industrial control system, and the like (collectively, “control systems”). Those networks utilize a unique combination of firewalls, intrusion detection systems, intrusion protection devices and/or other devices for hardening (e.g., security against hacking, intrusion or other mischievous conduct) and/or intrusion detection. The networks and methods have application, by way of example, in plants, sites and other facilities in which networks that support control systems interface with corporate, business or other networks.

8. 发明授权

US06167891A Temperature controlled degassification of deionized water for megasonic cleaning of semiconductor wafers 有权
标题翻译：用于超声波清洗半导体晶片的去离子水温度控制脱气
公开(公告)号：US06167891A
公开(公告)日：2001-01-02
申请号：US09318156
申请日：1999-05-25
申请人： Stephan Kudelka , David Rath
发明人： Stephan Kudelka , David Rath
IPC分类号： B08B312
CPC分类号： H01L21/67057 , B08B3/12 , B08B2203/002
摘要： A system is provided to prepare deionized water having a 100% saturated concentration of a gas, e.g., nitrogen, at a hot temperature, e.g., 50-85° C., and an attendant pressure, e.g., atmospheric pressure, to clean a semiconductor wafer, e.g., of silicon. The gas concentration of deionized water having a predetermined concentration of the gas at a cold temperature, e.g., 15-30° C., is adjusted in a degassifier chamber having a vacuum pump and a pressure sensor, to provide an under-saturated concentration of the gas at the cold temperature corresponding to the saturated concentration thereof at the hot temperature and attendant pressure. The adjusted gas concentration water is then heated in a heating vessel having a heater and a temperature sensor, to the hot temperature to form a hot bath having such saturated gas concentration to clean the wafer, e.g., in a cleaning tank under megasonic vibrations. A controller is connected to the pump, pressure sensor, heater and temperature sensor to control the chamber pressure and vessel temperature.
摘要翻译：提供一种系统来制备具有100％饱和浓度的气体（例如氮气）的去离子水，其在例如50-85℃的热温度和伴随的压力（例如大气压）下清洁半导体晶片，例如硅。在具有真空泵和压力传感器的脱气室中调节在例如15-30℃的冷温度下具有预定浓度的气体的去离子水的气体浓度，以提供不饱和的浓度在温度较低的温度下，与其饱和浓度对应的气体和伴随的压力。然后将经调节的气体浓度的水在具有加热器和温度传感器的加热容器中加热到热的温度，以形成具有饱和气体浓度的热浴，以清洁晶片，例如在超声波振动下的清洗槽中。控制器连接到泵，压力传感器，加热器和温度传感器，以控制腔室的压力和容器温度。

9. 发明申请

US20080284019A1 CONDUCTOR-DIELECTRIC STRUCTURE AND METHOD FOR FABRICATING 失效
标题翻译：导电介质结构和制造方法
公开(公告)号：US20080284019A1
公开(公告)日：2008-11-20
申请号：US12128713
申请日：2008-05-29
申请人： Chih-Chao Yang , Shom Ponoth , David Rath , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Shom Ponoth , David Rath , Keith Kwong Hon Wong
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76843 , H01L21/76865 , H01L21/76868 , H01L21/76873 , H01L2221/1089
摘要： A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.
摘要翻译：通过提供包括其中具有图案化特征的电介质层的结构来制造导体 - 电介质互连结构; 在所述图案化特征中的所述电介质层上沉积电镀种子层; 在通孔的电镀种子层上沉积牺牲种子层; 通过反向电镀减少牺牲种子层的厚度; 以及在所述图案化特征中的所述牺牲种子层上镀覆导电金属。还提供了其中具有通孔的电介质层; 图案化特征中的电介质层上的电镀种子层; 以及位于图案化特征中的不连续牺牲种子层。

10. 发明申请

US20060183056A1 Method for isotropic etching of copper 失效
公开(公告)号：US20060183056A1
公开(公告)日：2006-08-17
申请号：US11401898
申请日：2006-04-12
申请人： Emanuel Cooper , Bruce Furman , David Rath
发明人： Emanuel Cooper , Bruce Furman , David Rath
IPC分类号： G03F7/00
CPC分类号： C23G1/103 , C23C22/63 , C23F1/34 , H01L21/32134
摘要： Copper and copper alloys are etched to provide uniform and smooth surface by employing an aqueous composition that comprises an oxidant, a mixture of at least one weak complexant and at least one strong complexant for the copper or copper alloy, and water and has a pH of about 6 to about 12 so as to form an oxidized etch controlling layer and to uniformly remove the copper or copper alloy; and then removing the oxidized etch controlling layer with a non-oxidizing composition. Copper and copper alloy structure, having smooth upper surfaces are also provided.

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