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31. 发明授权

US07859112B2 Additional metal routing in semiconductor devices 有权
标题翻译：半导体器件中的附加金属布线
公开(公告)号：US07859112B2
公开(公告)日：2010-12-28
申请号：US11331951
申请日：2006-01-13
申请人： Terry McDaniel , James Green , Mark Fischer
发明人： Terry McDaniel , James Green , Mark Fischer
IPC分类号： H01L23/52
CPC分类号： H01L27/105 , H01L21/823475 , H01L21/823871 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11531 , H01L29/66545
摘要： Memory devices, such as DRAM memory devices, may include one or more metal layers above a local interconnect of the DRAM memory that make contact to lower gate regions of the memory device. As the size of semiconductor components decreases and circuit densities increase, the density of the metal routing in these upper metal layers becomes increasingly difficult to fabricate. By providing additional metal routing in the lower gate regions that may be coupled to the upper metal layers, the spacing requirements of the upper metal layers may be eased, while maintaining the size of the semiconductor device. In addition, the additional metal routing formed in the gate regions of the memory devices may be disposed parallel to other metal contacts in a strapping configuration, thus reducing a resistance of the metal contacts, such as buried digit lines of a DRAM memory cell.
摘要翻译：诸如DRAM存储器件的存储器件可以包括与存储器件的下部栅极区域接触的DRAM存储器的局部互连上方的一个或多个金属层。随着半导体元件的尺寸减小和电路密度增加，这些上层金属层中的金属布线的密度越来越难于制造。通过在可以耦合到上金属层的下栅极区域中提供额外的金属布线，可以在保持半导体器件的尺寸的同时，缓和上金属层的间隔要求。此外，形成在存储器件的栅极区域中的附加金属布线可以以带状构造平行于其它金属触点设置，从而减小金属触点（例如DRAM存储单元的埋置数字线）的电阻。

32. 发明授权

US06900138B1 Oxygen plasma treatment for nitride surface to reduce photo footing 有权
标题翻译：氧等离子体处理氮化物表面以减少照片基础
公开(公告)号：US06900138B1
公开(公告)日：2005-05-31
申请号：US09259762
申请日：1999-03-01
申请人： Zhiping Yin , Mark Fischer
发明人： Zhiping Yin , Mark Fischer
IPC分类号： H01L21/027 , H01L21/318 , H01L21/302
CPC分类号： H01L21/3185 , H01L21/0274
摘要： The present invention includes a method for preventing distortion in semiconductor fabrication. The method comprises providing a substrate comprising a film comprising silicon nitride. The substrate is treated in a vacuum of about 3.0-6.5 Torr in an atmosphere comprising oxygen plasma wherein the oxygen plasma flow rate is at least about 300 sccm oxygen. A resist is applied to the treated substrate and the resist is patterned over the treated substrate.
摘要翻译：本发明包括一种用于防止半导体制造中的变形的方法。该方法包括提供包含含氮化硅的膜的衬底。在包含氧等离子体的气氛中，在约3.0-6.5乇的真空中处理衬底，其中氧等离子体流速为至少约300sccm的氧气。将抗蚀剂施加到经处理的基底上，并且将抗蚀剂图案化在经处理的基底上。

33. 发明授权

US06677661B1 Semiconductive wafer assemblies 失效
标题翻译：半导体晶片组件
公开(公告)号：US06677661B1
公开(公告)日：2004-01-13
申请号：US09429220
申请日：1999-10-28
申请人： Scott Jeffrey DeBoer , John T. Moore , Mark Fischer , Randhir P. S. Thakur
发明人： Scott Jeffrey DeBoer , John T. Moore , Mark Fischer , Randhir P. S. Thakur
IPC分类号： H01L2358
CPC分类号： H01L21/28123 , H01L21/0276 , H01L21/31144 , H01L21/3185
摘要： In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the silicon nitride layer with silicon, the portion comprising less than or equal to about 95% of the thickness of the layer of silicon nitride. In another aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) increasing a refractive index of a first portion of the thickness of the silicon nitride layer relative to a refractive index of a second portion of the silicon nitride layer, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer. In yet another aspect, the invention includes semiconductor wafer assembly, comprising: a) a semiconductor wafer substrate; and b) a layer of silicon nitride over the substrate, the layer comprising a thickness and two portions elevationally displaced relative to one another, a first of the two portions having less resistance than a second of the two portions, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer.
摘要翻译：一方面，本发明包括半导体制造工艺，其包括：a）提供衬底; b）在衬底上形成氮化硅层，该层具有厚度; 以及c）用硅富集氮化硅层的一部分厚度，该部分包含小于或等于氮化硅层厚度的约95％。在另一方面，本发明包括半导体制造工艺，其包括：a）提供衬底; b）在衬底上形成氮化硅层，该层具有厚度; 以及c）相对于所述氮化硅层的第二部分的折射率增加所述氮化硅层的厚度的第一部分的折射率，所述第一部分包括小于或等于所述氮化硅层的厚度的约95％氮化硅层。在另一方面，本发明包括半导体晶片组件，包括：a）半导体晶片衬底; 以及b）在所述衬底上的一层氮化硅，所述层包括相对于彼此高度位移的厚度和两个部分，所述两个部分中的第一部分具有比所述两个部分中的第二部分更小的电阻，所述第一部分包括小于或等于氮化硅层厚度的约95％。

34. 发明授权

US06670288B1 Methods of forming a layer of silicon nitride in a semiconductor fabrication process 失效
标题翻译：在半导体制造工艺中形成氮化硅层的方法
公开(公告)号：US06670288B1
公开(公告)日：2003-12-30
申请号：US09604850
申请日：2000-06-27
申请人： Scott Jeffrey DeBoer , John T. Moore , Mark Fischer , Randhir P. S. Thakur
发明人： Scott Jeffrey DeBoer , John T. Moore , Mark Fischer , Randhir P. S. Thakur
IPC分类号： H01L2131
CPC分类号： H01L21/28123 , H01L21/0276 , H01L21/31144 , H01L21/3185
摘要： In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the silicon nitride layer with silicon, the portion comprising less than or equal to about 95% of the thickness of the layer of silicon nitride. In another aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) increasing a refractive index of a first portion of the thickness of the silicon nitride layer relative to a refractive index of a second portion of the silicon nitride layer, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer. In yet another aspect, the invention includes semiconductor wafer assembly, comprising: a) a semiconductor wafer substrate; and b) a layer of silicon nitride over the substrate, the layer comprising a thickness and two portions elevationally displaced relative to one another, a first of the two portions having less resistance than a second of the two portions, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer.
摘要翻译：一方面，本发明包括半导体制造工艺，其包括：a）提供衬底; b）在衬底上形成氮化硅层，该层具有厚度; 以及c）用硅富集氮化硅层的一部分厚度，该部分包含小于或等于氮化硅层厚度的约95％。在另一方面，本发明包括半导体制造工艺，其包括：a）提供衬底; b）在衬底上形成氮化硅层，该层具有厚度; 以及c）相对于所述氮化硅层的第二部分的折射率增加所述氮化硅层的厚度的第一部分的折射率，所述第一部分包括小于或等于所述氮化硅层的厚度的约95％氮化硅层。在另一方面，本发明包括半导体晶片组件，包括：a）半导体晶片衬底; 以及b）在所述衬底上的一层氮化硅，所述层包括相对于彼此高度位移的厚度和两个部分，所述两个部分中的第一部分具有比所述两个部分中的第二部分更小的电阻，所述第一部分包括小于或等于氮化硅层厚度的约95％。

35. 发明授权

US06440850B1 Structure for an electrical contact to a thin film in a semiconductor structure and method for making the same 有权
标题翻译：用于与半导体结构中的薄膜的电接触的结构及其制造方法
公开(公告)号：US06440850B1
公开(公告)日：2002-08-27
申请号：US09385586
申请日：1999-08-27
申请人： Kunal R. Parekh , Mark Fischer , Charles H. Dennison
发明人： Kunal R. Parekh , Mark Fischer , Charles H. Dennison
IPC分类号： H01L2144
CPC分类号： H01L23/485 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A network of electrically conductive plate contacts is provided within the structure of a DRAM chip to enable storage of non-zero voltage levels in each charge storage region. An improved cell or top plate contact provides low contact resistance and improved structural integrity making the contact less prone to removal during subsequent processing steps. A top plate conformally lines a container patterned down into a subregion. A metal contact structure comprises a waist section, a contact leg, and an anchor leg. The contact leg makes contact to the top plate within the container interior. The waist section joins the top of the contact leg to the top of the anchor leg and extends over the edge of the top plate. The anchor leg extends downward through the subregion adjacent to but spaced from the container to anchor the structure in place and provide structural integrity. Accordingly, the present invention provides an improved structure for contact to a conductive thin film, having low contact resistance and an improved structural integrity.
摘要翻译：在DRAM芯片的结构内提供导电板触点的网络，以便能够在每个电荷存储区域中存储非零电压电平。改进的电池或顶板接触提供低接触电阻和改进的结构完整性，使得接触在随后的加工步骤期间更不易于去除。顶板共形地将图案化的容器图案化成一个子区域。金属接触结构包括腰部，接触腿和锚腿。接触腿与容器内部的顶板接触。腰部将接触腿的顶部连接到锚腿的顶部并且在顶板的边缘上延伸。锚腿向下延伸穿过与容器相邻但与容器间隔开的子区域，以将结构锚定在适当位置并提供结构完整性。因此，本发明提供了一种与导电薄膜接触的改进的结构，具有低的接触电阻和改进的结构完整性。

36. 发明授权

US06376358B1 Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications 有权
公开(公告)号：US06376358B1
公开(公告)日：2002-04-23
申请号：US09809666
申请日：2001-03-15
申请人： Mark Fischer , Jigish D. Trivedi , Charles H. Dennison , Todd R. Abbott , Raymond A. Turi
发明人： Mark Fischer , Jigish D. Trivedi , Charles H. Dennison , Todd R. Abbott , Raymond A. Turi
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , G11C2207/104 , H01L21/76889 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10888
摘要： A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten are formed subsequent to polysilicon plugs required for the operation of the DRAM and SRAM or logic. Also disclosed are systems-on-chips MIM/MIS capacitive devices produced by the inventive process.

37. 发明授权

US06300253B1 Semiconductor processing methods of forming photoresist over silicon nitride materials, and semiconductor wafer assemblies comprising photoresist over silicon nitride materials 失效
标题翻译：在氮化硅材料上形成光刻胶的半导体加工方法以及包含氮化硅材料上的光致抗蚀剂的半导体晶片组件
公开(公告)号：US06300253B1
公开(公告)日：2001-10-09
申请号：US09057155
申请日：1998-04-07
申请人： John T. Moore , Scott J. DeBoer , Mark Fischer
发明人： John T. Moore , Scott J. DeBoer , Mark Fischer
IPC分类号： H01L2131
CPC分类号： H01L21/31144 , G03F7/091 , H01L21/0214 , H01L21/0217 , H01L21/02211 , H01L21/02271 , H01L21/02304 , H01L21/312
摘要： In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer. In another aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; c) forming a photoresist over and against the barrier layer; d) exposing the photoresist to a patterned beam of light to render at least one portion of the photoresist more soluble in a solvent than an other portion, the barrier layer being an antireflective surface that absorbs light passing through the photoresist; and e) exposing the photoresist to the solvent to remove the at least one portion while leaving the other portion over the barrier layer. In yet another aspect, the invention includes a semiconductor wafer assembly, comprising: a) a silicon nitride material, the material having a surface; b) a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) a photoresist over and against the barrier layer.
摘要翻译：一方面，本发明包括半导体处理方法，包括：a）提供具有表面的氮化硅材料; b）在所述材料的表面上形成阻挡层，所述阻挡层包含硅和氮; 以及c）在所述阻挡层上形成光致抗蚀剂。另一方面，本发明包括半导体处理方法，包括：a）提供具有表面的氮化硅材料; b）在所述材料的表面上形成阻挡层，所述阻挡层包含硅和氮; c）在阻挡层上形成光致抗蚀剂; d）将所述光致抗蚀剂暴露于图案化的光束以使所述光致抗蚀剂的至少一部分在溶剂中比其它部分更易溶，所述阻挡层是吸收通过所述光致抗蚀剂的光的抗反射表面; 以及e）将所述光致抗蚀剂暴露于所述溶剂以除去所述至少一个部分，同时将所述另一部分留在所述阻挡层上。在另一方面，本发明包括半导体晶片组件，包括：a）氮化硅材料，该材料具有表面; b）在所述材料的表面上的阻挡层，所述阻挡层包含硅和氮; 以及c）在所述阻挡层上并抵靠所述阻挡层的光致抗蚀剂。

38. 发明授权

US6083803A Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances 失效
公开(公告)号：US6083803A
公开(公告)日：2000-07-04
申请号：US32254
申请日：1998-02-27
申请人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
发明人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
IPC分类号： H01L21/302 , G03F7/075 , G03F7/16 , H01L21/3065 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10888 , G03F7/0757 , G03F7/167 , H01L21/76838 , H01L27/10852
摘要： Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug. In another aspect, conductive plug material is unevenly doped with dopant, and conductive plug material containing greater concentrations of dopant is etched at a greater rate than plug material containing lower concentrations of dopant.

39. 发明授权

US5962885A Method of forming a capacitor and a capacitor construction 失效
标题翻译：电容器结构
公开(公告)号：US5962885A
公开(公告)日：1999-10-05
申请号：US935966
申请日：1997-09-23
申请人： Mark Fischer , Mark Jost , Kunal Parekh
发明人： Mark Fischer , Mark Jost , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L28/40 , Y10S148/02
摘要： The invention encompasses capacitor constructions. In one aspect, the invention includes a stacked capacitor construction comprising: a) a substrate; b) an electrically conductive runner provided on the substrate, the runner having an outer conductive surface; c) a node on the substrate adjacent the electrically conductive runner; d) an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node adjacent the conductive runner, the pillar having an outer surface; e) an electrically conductive storage node container layer in electrical connection with the pillar; f) a capacitor dielectric layer over the capacitor storage node layer; and g) an electrically conductive outer capacitor plate over the capacitor dielectric layer; and h) the pillar outer surface being elevationally inward of the runner outer surface.
摘要翻译：本发明包括电容器结构。一方面，本发明包括堆叠式电容器结构，其包括：a）衬底; b）设置在所述基底上的导电流道，所述流道具有外导电表面; c）邻近导电流道的衬底上的节点; d）与所述节点电连接的导电柱，所述柱相对于邻近导电流道的节点向外突出，所述柱具有外表面; e）与所述支柱电连接的导电存储节点容器层; f）电容器存储节点层上的电容器介电层; 和g）电容器介电层上的导电外电容器板; 以及h）所述柱外表面位于所述流道外表面的正上方。

40. 发明授权

US5932491A Reduction of contact size utilizing formation of spacer material over resist pattern 失效
标题翻译：通过在抗蚀剂图案上形成隔离材料来减小接触尺寸
公开(公告)号：US5932491A
公开(公告)日：1999-08-03
申请号：US796399
申请日：1997-02-06
申请人： Phillip G. Wald , Mark Fischer , William A. Stanton
发明人： Phillip G. Wald , Mark Fischer , William A. Stanton
IPC分类号： H01L21/768 , H01L21/00
CPC分类号： H01L21/76831 , H01L21/76807
摘要： A method for forming a sidewall aligned contact structure without a hardmask layer. A semiconductor region is provided having an active area at an upper surface. An insulating layer is formed having an upper surface over the active area. Using a photo-patterned organic mask, a gross contact opening is etched in the insulating layer over the active area. The gross contact opening extends downward from the upper surface and partially through the insulating layer. A conformal layer of material is deposited at low temperature over the patterned mask as well as sidewalls and a bottom surface of the gross contact opening The conformal layer comprises a material that is differentially etchable with respect to the photomask and preferably etches similarly to the insulating layer. A portion of the insulating layer at the base of the gross contact opening is exposed. A contact opining is formed in the exposed portion of the insulating layer using the remaining conformal layer as a mask.
摘要翻译：一种用于形成没有硬掩模层的侧壁对齐接触结构的方法。提供在上表面具有有效面积的半导体区域。在有源区域上形成有上表面的绝缘层。使用光刻图案的有机掩模，在有效区域上的绝缘层中蚀刻总接触开口。总接触开口从上表面向下延伸并且部分地穿过绝缘层。在图案化掩模以及总接触开口的侧壁和底表面上的低温下沉积保形层材料。共形层包括相对于光掩模可差分蚀刻的材料，并且优选类似于绝缘层蚀刻。在总触点开口底部的绝缘层的一部分露出。使用剩余的保形层作为掩模，在绝缘层的暴露部分中形成接触形成。

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