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1. 发明授权

US6083803A Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances 失效
公开(公告)号：US6083803A
公开(公告)日：2000-07-04
申请号：US32254
申请日：1998-02-27
申请人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
发明人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
IPC分类号： H01L21/302 , G03F7/075 , G03F7/16 , H01L21/3065 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10888 , G03F7/0757 , G03F7/167 , H01L21/76838 , H01L27/10852
摘要： Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug. In another aspect, conductive plug material is unevenly doped with dopant, and conductive plug material containing greater concentrations of dopant is etched at a greater rate than plug material containing lower concentrations of dopant.

2. 发明授权

US06309973B1 Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances 失效
标题翻译：形成导电投影的半导体处理方法和增加对准公差的方法
公开(公告)号：US06309973B1
公开(公告)日：2001-10-30
申请号：US09507193
申请日：2000-02-18
申请人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
发明人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
IPC分类号： H01L21302
CPC分类号： H01L27/10888 , G03F7/0757 , G03F7/167 , H01L21/76838 , H01L27/10852
摘要： Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a, portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug. In another aspect, conductive plug material is unevenly doped with dopant, and conductive plug material containing greater concentrations of dopant is etched at a greater rate than plug material containing lower concentrations of dopant.
摘要翻译：描述形成导电突起的半导体加工方法和增加对准公差的方法。在一个实施方案中，导电突起形成在衬底表面区域上，并且包括与其连接的上表面和侧表面以限定拐角区域。导电突起的角区域随后被倒角以增加相对于其的对准公差。在另一实施方案中，导电插塞形成在一对导线之间的衬底节点位置之上并且具有最上表面。导电插塞的材料被不均匀地移除以限定第二最上表面，其中至少一部分的表面布置在高于导电线的高度上。在一个方面，可以通过刻蚀导电插塞去除导电插塞材料。在另一方面，导电插塞材料用掺杂剂不均匀掺杂，并且以比含有较低浓度掺杂剂的插塞材料更大的速率蚀刻含有较大浓度掺杂剂的导电插塞材料。

3. 发明授权

US07419913B2 Methods of forming openings into dielectric material 有权
标题翻译：将开口形成电介质材料的方法
公开(公告)号：US07419913B2
公开(公告)日：2008-09-02
申请号：US11217905
申请日：2005-09-01
申请人： Thomas M. Graettinger , John K. Zahurak , Shane J. Trapp , Thomas Arthur Figura
发明人： Thomas M. Graettinger , John K. Zahurak , Shane J. Trapp , Thomas Arthur Figura
IPC分类号： H01L21/461
CPC分类号： H01L21/31116 , H01L21/31122 , H01L21/31138 , H01L21/31144 , H01L21/76802 , H01L21/76844 , H01L27/10852
摘要： This invention includes methods of forming openings into dielectric material. In one implementation, an opening is partially etched through dielectric material, with such opening comprising a lowest point and opposing sidewalls of the dielectric material. At least respective portions of the opposing sidewalls within the opening are lined with an electrically conductive material. With such electrically conductive material over said respective portions within the opening, plasma etching is conducted into and through the lowest point of the dielectric material of the opening to extend the opening deeper within the dielectric material. Other aspects and implementations are contemplated.
摘要翻译：本发明包括在电介质材料中形成开口的方法。在一个实施方案中，通过电介质材料部分蚀刻开口，其中这种开口包括介电材料的最低点和相对的侧壁。开口内的相对侧壁的至少相应部分衬有导电材料。通过在开口内的所述各个部分上的这种导电材料，等离子体蚀刻被导入并通过开口的电介质材料的最低点，以使电介质材料内的开口更深。考虑了其他方面和实现。

4. 发明授权

US07687844B2 Semiconductor constructions 失效
标题翻译：半导体结构
公开(公告)号：US07687844B2
公开(公告)日：2010-03-30
申请号：US12052124
申请日：2008-03-20
申请人： Cancheepuram V. Srividya , F. Daniel Gealy , Thomas M. Graettinger
发明人： Cancheepuram V. Srividya , F. Daniel Gealy , Thomas M. Graettinger
IPC分类号： H01L27/108
CPC分类号： H01L28/65 , H01L27/1085 , H01L27/10852 , H01L27/1087 , H01L28/84 , H01L29/66181
摘要： The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second regions are exposed to a mixture comprising a precursor of a noble metal and an oxidant. During the exposure, a layer containing the noble metal is selectively deposited onto the first region relative to the second region. In particular applications, the first region can comprise borophosphosilicate glass, and the second region can comprise either aluminum oxide or doped non-oxidized silicon. The invention also includes capacitor constructions and methods of forming capacitor constructions.
摘要翻译：本发明包括沉积贵金属的方法。提供基板。衬底具有第一区域和第二区域。第一和第二区域暴露于包含贵金属和氧化剂的前体的混合物中。在曝光期间，包含贵金属的层相对于第二区域选择性地沉积在第一区域上。在具体应用中，第一区域可以包括硼磷硅酸盐玻璃，并且第二区域可以包括氧化铝或掺杂的非氧化硅。本发明还包括电容器结构和形成电容器结构的方法。

5. 发明申请

US20080045034A1 Methods for forming semiconductor constructions, and methods for selectively etching silicon nitride relative to conductive material 有权
标题翻译：用于形成半导体结构的方法以及相对于导电材料选择性地蚀刻氮化硅的方法
公开(公告)号：US20080045034A1
公开(公告)日：2008-02-21
申请号：US11506347
申请日：2006-08-17
申请人： Kevin R. Shea , Thomas M. Graettinger
发明人： Kevin R. Shea , Thomas M. Graettinger
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L28/92 , H01L21/30625 , H01L21/31116 , H01L21/31144 , H01L21/32139 , H01L27/105 , H01L27/1052 , H01L27/108
摘要： The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
摘要翻译：本发明包括相对于导电材料选择性地蚀刻绝缘材料支撑件的方法。本发明可以包括相对于金属氮化物选择性地蚀刻氮化硅的方法。金属氮化物可以是在半导体衬底上的容器的形式，其中这种容器具有向上延伸的开口，横向宽度小于或等于约4000埃; 并且氮化硅可以是在容器之间延伸的层的形式。选择性蚀刻可以包括将氮化硅和容器中的至少一些暴露于Cl 2以除去暴露的氮化硅，同时不从容器中去除至少大部分金属氮化物。在随后的处理中，容器可以并入电容器中。

6. 发明授权

US07226845B2 Semiconductor constructions, and methods of forming capacitor devices 有权
公开(公告)号：US07226845B2
公开(公告)日：2007-06-05
申请号：US11215243
申请日：2005-08-30
申请人： H. Montgomery Manning , Thomas M. Graettinger
发明人： H. Montgomery Manning , Thomas M. Graettinger
IPC分类号： H01L21/331
CPC分类号： H01L27/10894 , H01L27/10817 , H01L27/10852 , H01L28/91 , H01L29/945 , Y10S257/906
摘要： The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.

7. 发明授权

US06881642B2 Method of forming a MIM capacitor with metal nitride electrode 失效
标题翻译：用金属氮化物电极形成MIM电容器的方法
公开(公告)号：US06881642B2
公开(公告)日：2005-04-19
申请号：US10419191
申请日：2003-04-21
申请人： Cem Basceri , Thomas M. Graettinger
发明人： Cem Basceri , Thomas M. Graettinger
IPC分类号： H01L21/02 , H01L21/285 , H01L21/316 , H01L21/20
CPC分类号： H01L28/84 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/02194 , H01L21/0228 , H01L21/28568 , H01L21/3162 , H01L28/75 , H01L28/90
摘要： A method of forming an MIM capacitor with low leakage and high capacitance is disclosed. A layer of titanium nitride (TiN) or boron-doped titanium nitride (TiBN) material is formed as a lower electrode over an optional capacitance layer of hemispherical grained polysilicon (HSG). Prior to the dielectric formation, the first layer may be optionally subjected to a nitridization or oxidation process. A dielectric layer of, for example, aluminum oxide (Al2O3) formed by atomic layer deposition (ALD) is fabricated over the first layer and after the optional nitridization or oxidation process. An upper electrode of titanium nitride (TiN) or boron-doped titanium nitride (TiBN) is formed over the dielectric layer.
摘要翻译：公开了一种形成具有低泄漏和高电容的MIM电容器的方法。在半球状晶粒多晶硅（HSG）的可选电容层上形成氮化钛（TiN）或硼掺杂氮化钛（TiBN）材料层作为下电极。在电介质形成之前，第一层可以任选地进行氮化或氧化过程。通过原子层沉积（ALD）形成的例如氧化铝（Al 2 O 3 N）的电介质层在第一层上和在任选的氮化之后制造，或氧化过程。在电介质层上形成氮化钛（TiN）或硼掺杂氮化钛（TiBN）的上电极。

8. 发明授权

US06858894B2 Comprising agglomerates of one or more noble metals 失效
标题翻译：包含一种或多种贵金属的附聚物
公开(公告)号：US06858894B2
公开(公告)日：2005-02-22
申请号：US10773780
申请日：2004-02-09
申请人： Cancheepuram V. Srividya , F. Daniel Gealy , Thomas M. Graettinger
发明人： Cancheepuram V. Srividya , F. Daniel Gealy , Thomas M. Graettinger
IPC分类号： H01L21/02 , H01L21/334 , H01L21/4763 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/65 , H01L27/1085 , H01L27/10852 , H01L27/1087 , H01L28/84 , H01L29/66181
摘要： The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second regions are exposed to a mixture comprising a precursor of a noble metal and an oxidant. During the exposure, a layer containing the noble metal is selectively deposited onto the first region relative to the second region. In particular applications, the first region can comprise borophosphosilicate glass, and the second region can comprise either aluminum oxide or doped non-oxidized silicon. The invention also includes capacitor constructions and methods of forming capacitor constructions.
摘要翻译：本发明包括沉积贵金属的方法。提供基板。衬底具有第一区域和第二区域。第一和第二区域暴露于包含贵金属和氧化剂的前体的混合物中。在曝光期间，包含贵金属的层相对于第二区域选择性地沉积在第一区域上。在具体应用中，第一区域可以包括硼磷硅酸盐玻璃，并且第二区域可以包括氧化铝或掺杂的非氧化硅。本发明还包括电容器结构和形成电容器结构的方法。

9. 发明授权

US06297124B1 Method of improving alignment signal strength by reducing refraction index at interface of materials in semiconductors 有权
$Method of improving alignment signal strength by reducing refraction index at interface of materials in semiconductors$
标题翻译：通过减少半导体材料界面处的折射率来提高取向信号强度的方法
公开(公告)号：US06297124B1
公开(公告)日：2001-10-02
申请号：US09395724
申请日：1999-09-14
申请人： Daryl C. New , Thomas M. Graettinger
发明人： Daryl C. New , Thomas M. Graettinger
IPC分类号： H01L2176
CPC分类号： G03F9/7076 , G03F9/7084 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a first layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the first layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers. The aforementioned method and resulting structures can be further modified by forming an additional layer of material, having the requisite intermediate index of refraction, over an uppermost layer to further reduce reflection occurring at the interface between the uppermost layer and air. The invention is also directed to semiconductor devices, assemblies or laminates formed through the aforementioned methods and incorporating the aforementioned structures.
摘要翻译：一种用于在半导体器件制造工艺中的对准步骤期间在半导体器件，组件或层压体中的不同材料的相邻层之间的界面处发生折射和反射的方法和结果。该方法包括在半导体器件的衬底，组件或层压体上形成具有第一折射率的第一材料层。在第一层上形成校正层，然后在校正层上形成具有第二折射率的第二层。校正层由在第一折射率和第二折射率之间具有中间折射率的材料组成。该方法还可以被修改为包括插入在任何上述相邻层之间或之上的一层或多层材料和/或中间折射层。可以通过在最上层上形成具有必要的中间折射率的附加材料层来进一步改进上述方法和所得结构，以进一步减少在最上层与空气之间的界面处发生的反射。本发明还涉及通过上述方法形成并结合上述结构的半导体器件，组件或层压体。

10. 发明申请

US20120168903A1 Semiconductor Constructions Containing Tubular Capacitor Storage Nodes, And Retaining Structures Along Portions Of The Tubular Capacitor Storage Nodes 有权
标题翻译：包含管状电容器存储节点和保留结构的半导体结构沿管状电容器存储节点的一部分
公开(公告)号：US20120168903A1
公开(公告)日：2012-07-05
申请号：US13413552
申请日：2012-03-06
申请人： H. Montgomery Manning , Thomas M. Graettinger
发明人： H. Montgomery Manning , Thomas M. Graettinger
IPC分类号： H01L29/02
CPC分类号： H01L27/10894 , H01L27/10817 , H01L27/10852 , H01L28/91 , H01L29/945 , Y10S257/906
摘要： The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.
摘要翻译：本发明包括半导体结构，并且还包括形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电储存节点材料以形成导电容器。形成与至少一些容器物理接触的保持结构格子，随后去除绝缘材料以露出容器的外表面。保持结构可以减轻容器结构的结构完整性的倒塌或其它损失。导电容器对应于第一电容器电极。在容器的外侧壁暴露之后，电介质材料形成在容器内并沿外露的外侧壁。随后，在电介质材料上形成第二电容器电极。第一和第二电容器电极与电介质材料一起形成多个电容器器件。

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