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31. 发明授权

US06665350B1 Method and system for improved analog signal detection 失效
标题翻译：改进模拟信号检测方法和系统
公开(公告)号：US06665350B1
公开(公告)日：2003-12-16
申请号：US09160484
申请日：1998-09-25
申请人： John G. Bartkowiak
发明人： John G. Bartkowiak
IPC分类号： H04L2710
CPC分类号： H04L27/30 , H04L27/0012
摘要： A method and system for improved detection of analog signals, where the analog signals may be composed of one or more analog frequencies. In the method and system, an analog signal is received. A stream of data samples is created from the analog signal. Based on the stream of data samples, a confidence factor regarding the presence of the one or more analog signals is created. The confidence factor is created based upon a confidence factor calculated for each of the one or more analog frequency signals. The confidence factor calculated for each of the one or more analog frequency signals is calculated utilizing incremental energies associated with each of the one or more analog frequency signals.
摘要翻译：一种用于改进模拟信号检测的方法和系统，其中模拟信号可以由一个或多个模拟频率组成。在该方法和系统中，接收模拟信号。从模拟信号创建数据采样流。基于数据样本流，产生关于一个或多个模拟信号的存在的置信因子。基于为一个或多个模拟频率信号中的每一个计算的置信因子创建置信因子。使用与一个或多个模拟频率信号中的每一个相关联的增量能量来计算针对一个或多个模拟频率信号中的每一个计算的置信因子。

32. 发明授权

US06574334B1 Efficient dynamic energy thresholding in multiple-tone multiple frequency detectors 失效
标题翻译：多频多频检波器中的高效动态能量门限
公开(公告)号：US06574334B1
公开(公告)日：2003-06-03
申请号：US09160417
申请日：1998-09-25
申请人： John G. Bartkowiak
发明人： John G. Bartkowiak
IPC分类号： H04M115
CPC分类号： H04M1/72
摘要： An apparatus for determining energy threshold detection values for detecting at least one tone having a known frequency and duration in an input signal. The input signal is input over a period of time that is divided into frame portions including at least an initial frame portion and a last frame portion. An energy value is determined for the at least one tone during each frame portion. A set of control flag signals are set for the at least two frame portions based on the energy values being below a threshold value in previous frame portions and the presence of noise in previous frame portions. An offset into a data table is determined based on the control word, the offset being used to retrieve a scaling coefficient and an address of an energy value for the at least two frame portions from the data table. A second set of control flag signals provide information on the number of comparisons to energy values from previous frames that are required to determine the energy threshold detection value for each frame portion.
摘要翻译：一种用于确定用于检测输入信号中具有已知频率和持续时间的至少一种音调的能量阈值检测值的装置。输入信号经过一段时间被输入，该时间段被分成包括至少初始帧部分和最后帧部分的帧部分。在每个帧部分期间为至少一个音调确定能量值。基于在先前帧部分中的能量值低于阈值并且在先前帧部分中存在噪声来为至少两个帧部分设置一组控制标志信号。基于控制字来确定对数据表的偏移量，所述控制字用于从数据表中检索缩放系数和至少两个帧部分的能量值的地址。第二组控制标志信号提供关于确定每个帧部分的能量阈值检测值所需的来自先前帧的能量值的比较数量的信息。

33. 发明授权

US5937374A System and method for improved pitch estimation which performs first formant energy removal for a frame using coefficients from a prior frame 失效
标题翻译：用于改进音调估计的系统和方法，其使用来自先前帧的系数对帧执行第一共振峰能量去除
公开(公告)号：US5937374A
公开(公告)日：1999-08-10
申请号：US647843
申请日：1996-05-15
申请人： John G. Bartkowiak , Mark A. Ireton
发明人： John G. Bartkowiak , Mark A. Ireton
IPC分类号： G10L11/04 , G10L19/08 , G10L3/02
CPC分类号： G10L25/90 , G10L19/08 , G10L19/09 , G10L25/06 , G10L25/15
摘要： An improved vocoder system and method for estimating pitch in a speech waveform which pre-filters speech data with improved efficiency and reduced computational requirements. The vocoder system is preferably a low bit rate speech coder which analyzes a plurality of frames of speech data in parallel. Once the LPC filter coefficients and the pitch for a first frame have been calculated, the vocoder then looks ahead to the next frame to estimate the pitch, i.e., to estimate the pitch of the next frame. In the preferred embodiment of the invention, the vocoder filters speech data in a second frame using a plurality of the coefficients from a first frame as a multi pole analysis filter. These coefficients are used as a "crude" two pole analysis filter. The vocoder preferably includes a first processor which performs coefficient calculations for the second frame, and a second processor which performs pre-filtering and pitch estimation, wherein the second processor operates substantially simultaneously with the first processor. Thus, the vocoder system uses LPC coefficients for a first frame as a "crude" multi pole analysis filter for a subsequent frame of data, thereby performing pre-filtering on a frame without requiring previous coefficient calculations for that frame. This allows pre-filtered pitch estimation and LPC coefficient calculations to be performed in parallel. This provides a more efficient pitch estimation, thus enhancing vocoder performance.
摘要翻译：一种用于估计语音波形中的音调的改进的声码器系统和方法，其以提高的效率和减少的计算要求预处理语音数据。声码器系统优选地是并行分析多个语音数据帧的低比特率语音编码器。一旦已经计算了LPC滤波器系数和第一帧的音调，则声码器然后前瞻到下一帧以估计音调，即估计下一帧的音高。在本发明的优选实施例中，声码器使用来自第一帧的多个系数作为多极分析滤波器对第二帧中的语音数据进行滤波。这些系数用作“粗”双极分析滤波器。声码器优选地包括执行第二帧的系数计算的第一处理器和执行预滤波和音调估计的第二处理器，其中第二处理器与第一处理器基本同时地操作。因此，声码器系统将第一帧的LPC系数用作随后的数据帧的“粗”多极分析滤波器，由此对帧执行预滤波，而不需要对该帧进行先前的系数计算。这允许并行执行预滤波的音调估计和LPC系数计算。这提供了更有效的音调估计，从而增强了声码器的性能。

34. 发明授权

US5809133A DTMF detector system and method which performs frequency domain energy calculations with improved performance 失效
标题翻译： DTMF检测器系统和方法，其具有改进的性能执行频域能量计算
公开(公告)号：US5809133A
公开(公告)日：1998-09-15
申请号：US653283
申请日：1996-05-24
申请人： John G. Bartkowiak , Zheng-yi Xie
发明人： John G. Bartkowiak , Zheng-yi Xie
IPC分类号： H04L27/30 , H04Q1/453 , H04Q1/457 , H04M3/00
CPC分类号： H04Q1/457 , H04L27/30 , H04Q1/453
摘要： An improved dual tone multifrequency (DTMF) or multitone signal detector which more efficiently detects DTMF signals. For each received frame, the present invention initially performs only a portion of the Goertzel DFT algorithm for each of the possible tone frequencies and then analyzes the interim accumulated energies. The DTMF detector then selects one or more frequencies from each of the tone groups which have the largest energy values, and the detector only completes calculation of the Goertzel DFT algorithm on those selected one or more frequencies. In other words, the DTMF detector discontinues calculation of the Goertzel DFT algorithm on one or more frequencies which have low accumulated interim energies. This reduces the computational requirements and provides improved performance.
摘要翻译：改进的双音多频（DTMF）或多音信号检测器，可更有效地检测DTMF信号。对于每个接收的帧，本发明最初仅针对每个可能的音调频率执行Goertzel DFT算法的一部分，然后分析临时累积的能量。然后，DTMF检测器从具有最大能量值的每个音调组中选择一个或多个频率，并且检测器仅完成所选择的一个或多个频率上的Goertzel DFT算法的计算。换句话说，DTMF检测器在具有低累积临时能量的一个或多个频率上中断对Goertzel DFT算法的计算。这减少了计算需求并提供了改进的性能。

35. 发明授权

US5784640A CPU with DSP function preprocessor having look-up table for translating instruction sequences intended to perform DSP function into DSP macros 失效
标题翻译：具有DSP功能预处理器的CPU具有用于将用于将DSP功能执行为DSP宏的指令序列的查找表
公开(公告)号：US5784640A
公开(公告)日：1998-07-21
申请号：US618241
申请日：1996-03-18
申请人： Saf Asghar , Mark Ireton , John G. Bartkowiak
发明人： Saf Asghar , Mark Ireton , John G. Bartkowiak
IPC分类号： G06F9/318 , G06F9/38 , G06F9/30 , G06F15/163
CPC分类号： G06F9/3017 , G06F9/3879 , G06F9/3885 , H04Q2213/13036 , H04Q2213/1305 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13107 , H04Q2213/13199 , H04Q2213/13299 , H04Q2213/13389 , H04Q2213/13396
摘要： A CPU or microprocessor which includes a general purpose CPU, such as an X86 core, and a DSP. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X8 opcode sequences and determines if a DSP function is being executed. The function preprocessor includes a look-up table which stores instruction sequences which implement DSP functions. Each pattern in the look-up table is compared with an instruction sequence to determine if one of the patterns substantially matches the instruction sequence. If the DSP function preprocessor determines that a DSP function is being executed, the DSP function preprocessor converts the opcodes to a DSP macro instruction that is provided to the DSP. The DSP executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core. Thus, the DSP offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSPs. Thus the present invention is backwards compatible with existing software.
摘要翻译：包括通用CPU（如X86内核）和DSP的CPU或微处理器。 CPU还包括智能DSP功能解码器或预处理器，用于检查X8操作码序列，并确定DSP功能是否正在执行。功能预处理器包括一个查找表，其存储执行DSP功能的指令序列。将查找表中的每个模式与指令序列进行比较，以确定其中一个模式是否基本上与指令序列匹配。如果DSP功能预处理器确定正在执行DSP功能，则DSP功能预处理器将操作码转换为提供给DSP的DSP宏指令。 DSP响应于宏指令，执行一个或多个DSP指令来实现所需的DSP功能。如果指令高速缓存或指令存储器中的X86操作码未指示或不打算执行DSP类型功能，则将操作码提供给X86内核。因此，DSP从X86内核中卸载这些数学函数，从而提高系统性能。 DSP与X86内核并行运行，提供进一步的性能优势。因此，本发明的CPU比X86逻辑更有效地实现DSP功能，而不需要额外的X86操作码。本发明还生成根据包括X86和DSP的本发明的仅在X86仅CPU或CPU上透明地操作的代码。因此，本发明与现有软件向后兼容。

36. 发明授权

US5754878A CPU with DSP function preprocessor having pattern recognition detector that uses table for translating instruction sequences intended to perform DSP function into DSP macros 失效
标题翻译：具有DSP功能预处理器的CPU具有模式识别检测器，其使用用于将用于将DSP功能执行到DSP宏的指令序列进行转换的表
公开(公告)号：US5754878A
公开(公告)日：1998-05-19
申请号：US618242
申请日：1996-03-18
申请人： Saf Asghar , Mark Ireton , John G. Bartkowiak
发明人： Saf Asghar , Mark Ireton , John G. Bartkowiak
IPC分类号： G06F9/318 , G06F9/38 , G06F15/78 , G06F9/30 , G06F15/163
CPC分类号： G06F9/382 , G06F15/7857 , G06F9/3017 , G06F9/3879 , G06F9/3885
摘要： A CPU or microprocessor which includes a general purpose CPU, such as an X86 core, and a DSP. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. The function preprocessor includes a pattern recognition detector which stores instruction sequences which implement DSP functions. The pattern recognition detector compares each pattern with an instruction sequence and determines if one of the patterns substantially matches the instruction sequence. If the DSP function preprocessor determines that a DSP function is being executed, the preprocessor converts or maps the opcodes to a DSP macro instruction that is provided to the DSP. The DSP executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. Thus, the DSP offloads these mathematical functions from the X86 core, thereby increasing system performance. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSPs. Thus the present invention is backwards compatible with existing software.
摘要翻译：包括通用CPU（如X86内核）和DSP的CPU或微处理器。 CPU还包括智能DSP功能解码器或预处理器，用于检查X86操作码序列，并确定DSP功能是否正在执行。功能预处理器包括存储执行DSP功能的指令序列的模式识别检测器。模式识别检测器将每个模式与指令序列进行比较，并确定模式之一是否基本上与指令序列一致。如果DSP功能预处理器确定正在执行DSP功能，则预处理器将操作码转换或映射到提供给DSP的DSP宏指令。 DSP响应于宏指令，执行一个或多个DSP指令来实现所需的DSP功能。如果指令高速缓存或指令存储器中的X86操作码不指示或不旨在执行DSP类型功能，则将操作码提供给当前现有技术计算机系统中发生的X86内核。因此，DSP从X86内核中卸载这些数学函数，从而提高系统性能。因此，本发明的CPU比X86逻辑更有效地实现DSP功能，而不需要额外的X86操作码。本发明还生成根据包括X86和DSP的本发明的仅在X86仅CPU或CPU上透明地操作的代码。因此，本发明与现有软件向后兼容。

37. 发明授权

US5732251A DSP with register file and multi-function instruction sequencer for vector processing by MACU 失效
标题翻译： DSP具有寄存器文件和多功能指令序列器，用于由MACU进行矢量处理
公开(公告)号：US5732251A
公开(公告)日：1998-03-24
申请号：US643342
申请日：1996-05-06
申请人： John G. Bartkowiak
发明人： John G. Bartkowiak
IPC分类号： G06F9/30 , G06F9/38 , G06F17/10
CPC分类号： G06F9/30141 , G06F9/3885
摘要： A DSP including a register file connected to data memories and functional units is provided. Functional units read operands from the register file and store results into the register file. Various register storage locations form communicative links between the functional units and the memories, in accordance with a particular code sequence being executed by the DSP. Because each functional unit has an independent path to the register file, each functional unit may provide results to the register file concurrently. Additionally, having multiple register storage locations which are accessible to any functional unit permits flexibility in the operation of the DSP. Multiple register storage locations may be used by the same functional unit, allowing program code to be more optimized by storing values for later use in one of the register storage locations, as opposed to storing values in the data memories. The register file essentially provides a buffer between the functional units, and between the functional units and memory.
摘要翻译：提供了包括连接到数据存储器和功能单元的寄存器文件的DSP。功能单元从寄存器文件中读取操作数，并将结果存储到寄存器文件中。根据由DSP执行的特定代码序列，各种寄存器存储位置形成功能单元和存储器之间的通信链路。因为每个功能单元具有到寄存器文件的独立路径，所以每个功能单元可以同时向寄存器文件提供结果。此外，具有可由任何功能单元访问的多个寄存器存储单元允许DSP的操作的灵活性。多个寄存器存储位置可以由相同的功能单元使用，通过将值存储在一个寄存器存储位置中，以便将数据存储在数据存储器中，从而允许程序代码被更优化以供稍后使用。寄存器文件本质上在功能单元之间以及功能单元和存储器之间提供缓冲器。

38. 发明授权

US5555287A Integrated circuit and cordless telephone using the integrated circuit 失效
标题翻译：集成电路和无绳电话采用集成电路
公开(公告)号：US5555287A
公开(公告)日：1996-09-10
申请号：US918627
申请日：1992-07-21
申请人： Dale E. Gulick , Joseph W. Peterson , James E. Bowles , John G. Bartkowiak , Munehiro Yoshikawa , Shin Saito , Hiroshi Matsubara
发明人： Dale E. Gulick , Joseph W. Peterson , James E. Bowles , John G. Bartkowiak , Munehiro Yoshikawa , Shin Saito , Hiroshi Matsubara
IPC分类号： H04Q7/32 , G06F11/00 , G06F11/26 , H04B1/40 , H04M1/00 , H04M1/725 , H04M1/73 , H04Q7/38
CPC分类号： H04M1/73 , H04B1/40 , H04M1/725 , G06F11/0757 , G06F11/261
摘要： An integrated circuit especially suitable for incorporation into the base and handset units of a cordless telephone integrates the speech, control channels, and microcontroller portions of a modem, and the man-machine interface functions of a cordless telephone. The integrated circuit includes one or more of a number of aspects including an in-circuit emulation mechanism, a simplified keypad reporting mechanism, advanced noise suppression mechanisms, a low power emergency mode mechanism, a low cost serial control bus, a port pin interrupt mechanism, advanced power saving mechanisms, spectral measurement test mode means, a novel shut down mechanism, and a pull-up disabling mechanism.
摘要翻译：特别适用于并入无绳电话的基座和手机单元的集成电路集成了调制解调器的语音，控制信道和微控制器部分，以及无绳电话的人机接口功能。集成电路包括多个方面中的一个或多个，包括在线仿真机制，简化的键盘报告机制，高级噪声抑制机制，低功率紧急模式机制，低成本串行控制总线，端口引脚中断机制先进的省电机制，光谱测量测试模式，新型关机机制和上拉禁用机制。

39. 发明授权

US5347480A Digital signal processing apparatus 失效
标题翻译：数字信号处理装置
公开(公告)号：US5347480A
公开(公告)日：1994-09-13
申请号：US53959
申请日：1993-04-27
申请人： Safdar M. Asghar , John G. Bartkowiak , Michael A. Nix
发明人： Safdar M. Asghar , John G. Bartkowiak , Michael A. Nix
IPC分类号： G06F7/52 , G06F7/523 , G06F7/53 , G06F7/544 , G06F9/302 , G06F9/318 , G06F17/10 , G06F15/00
CPC分类号： G06F17/10 , G06F7/5443 , G06F9/30014 , G06F9/30167 , G06F9/30181
摘要： An apparatus for processing a received signal according to a digital signal processing algorithm having a multiplier and a limit and quantization circuit appropriately connected within the apparatus to permit operation of the multiplier and the limit and quantization circuit in parallel with logic processing by the apparatus. The address bus system of the apparatus is connected to the parallel-connected components and conveys instructions to the parallel-connected components, at least in part, by predetermined address information via the address bus system.
摘要翻译：一种用于根据数字信号处理算法处理接收信号的装置，该数字信号处理算法具有在装置内适当连接的乘法器和限制量化电路，以允许乘法器和极限量化电路与该装置的逻辑处理并行进行操作。该设备的地址总线系统连接到并联连接的组件，并且至少部分地通过地址总线系统通过预定的地址信息将指令传送到并联连接的组件。

40. 发明授权

US4994801A Apparatus adaptable for use in effecting communications between an analog device and a digital device 失效
标题翻译：适用于实现模拟设备和数字设备之间的通信的设备
公开(公告)号：US4994801A
公开(公告)日：1991-02-19
申请号：US428614
申请日：1989-10-30
申请人： Safdar M. Asghar , John G. Bartkowiak , Miki Z. Moyal
发明人： Safdar M. Asghar , John G. Bartkowiak , Miki Z. Moyal
IPC分类号： H03H17/06
CPC分类号： H03H17/0444 , H03H17/0621 , H03H17/0664
摘要： An apparatus adaptable for use in effecting communications between an analog device and a digital device, having an analog-digital-analog circuit for converting incoming analog signals received from the analog device to incoming digital signals, and for converting interpolated outgoing digital signals to outgoing analog signals. The apparatus further has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device, and for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal to the analog-digital-analog device. The analog-digital-analog device includes a single digital-to-analog converter and switches for selectively configuring the analog-digital-analog circuit to effect conversion of incoming analog signals to incoming digital signals or, alternatively, to effect conversion of interpolated outgoing digital signals to outgoing analog signals. The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of decimation and a specified number of iterations of interpolation. Certain of the specified set of modules participate in both the decimation and interpolation operations. The modules are further designed so that additional modules may be added to the specified set of modules to increase the iterations of decimation or to increase the iterations of interpolation, or to increase the iterations of both decimation and interpolation.
摘要翻译：一种适于用于实现模拟设备和数字设备之间的通信的设备，具有用于将从模拟设备接收的输入模拟信号转换为输入数字信号的模拟数字模拟电路，以及用于将内插输出数字信号转换为输出模拟信号。该装置还具有数字信号处理电路，用于抽取输入的数字信号并向数字装置提供抽取的输入数字信号，并且用于内插从数字装置接收到的输出数字信号，并将内插的输出数字信号提供给模拟数字 -analog设备。模拟数字模拟设备包括单个数模转换器和开关，用于选择性地配置模拟数字模拟电路以实现输入模拟信号到输入数字信号的转换，或者替代地，实现内插输出数字信号输出模拟信号。数字信号处理电路包括多个模块，其被配置为使得多个模块的指定集合实现特定数量的抽取迭代次数和指定次数的内插迭代。指定的一组模块中的某些参与抽取和插值操作。这些模块被进一步设计，使得附加的模块可以被添加到指定的模块集合中，以增加抽取的迭代或增加内插的迭代，或增加抽取和插值的迭代。

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