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1. 发明授权

US5555287A Integrated circuit and cordless telephone using the integrated circuit 失效
标题翻译：集成电路和无绳电话采用集成电路
公开(公告)号：US5555287A
公开(公告)日：1996-09-10
申请号：US918627
申请日：1992-07-21
申请人： Dale E. Gulick , Joseph W. Peterson , James E. Bowles , John G. Bartkowiak , Munehiro Yoshikawa , Shin Saito , Hiroshi Matsubara
发明人： Dale E. Gulick , Joseph W. Peterson , James E. Bowles , John G. Bartkowiak , Munehiro Yoshikawa , Shin Saito , Hiroshi Matsubara
IPC分类号： H04Q7/32 , G06F11/00 , G06F11/26 , H04B1/40 , H04M1/00 , H04M1/725 , H04M1/73 , H04Q7/38
CPC分类号： H04M1/73 , H04B1/40 , H04M1/725 , G06F11/0757 , G06F11/261
摘要： An integrated circuit especially suitable for incorporation into the base and handset units of a cordless telephone integrates the speech, control channels, and microcontroller portions of a modem, and the man-machine interface functions of a cordless telephone. The integrated circuit includes one or more of a number of aspects including an in-circuit emulation mechanism, a simplified keypad reporting mechanism, advanced noise suppression mechanisms, a low power emergency mode mechanism, a low cost serial control bus, a port pin interrupt mechanism, advanced power saving mechanisms, spectral measurement test mode means, a novel shut down mechanism, and a pull-up disabling mechanism.
摘要翻译：特别适用于并入无绳电话的基座和手机单元的集成电路集成了调制解调器的语音，控制信道和微控制器部分，以及无绳电话的人机接口功能。集成电路包括多个方面中的一个或多个，包括在线仿真机制，简化的键盘报告机制，高级噪声抑制机制，低功率紧急模式机制，低成本串行控制总线，端口引脚中断机制先进的省电机制，光谱测量测试模式，新型关机机制和上拉禁用机制。

2. 发明授权

US5502689A Clock generator capable of shut-down mode and clock generation method 失效
标题翻译：具有关闭模式和时钟发生方式的时钟发生器
公开(公告)号：US5502689A
公开(公告)日：1996-03-26
申请号：US201077
申请日：1994-02-24
申请人： Joseph W. Peterson , Alan F. Hendrickson , Dale E. Gulick , Dean Grumlose
发明人： Joseph W. Peterson , Alan F. Hendrickson , Dale E. Gulick , Dean Grumlose
IPC分类号： H04B1/16 , G06F1/04 , G06F1/32 , H04B1/38 , H04B7/26 , G04F5/00 , G06F1/00
CPC分类号： G06F1/3287 , G06F1/3203 , Y02B60/1282 , Y02B60/32
摘要： A clock generator and interrupt bypass circuit for use in reducing the power consumption of the electrical system in which they are implemented. The clock generator provides module clock signals for sequencing modules within the same electrical system, and is capable of generating those module clock signals when in an active mode, and of not generating those module clock signals when in a stand-by mode. The clock generator is further capable of providing a delay of a predetermined length from a request to enter shut-down mode to actual entry into shut-down mode, allowing time to prepare the electrical system for shut-down mode. The interrupt bypass circuit provides a means of leaving shut-down mode in the event that the relevant interrupt requests have been masked.
摘要翻译：一个时钟发生器和中断旁路电路，用于降低实施电气系统的功耗。时钟发生器为同一电气系统中的排序模块提供模块时钟信号，并且能够在处于活动模式时产生那些模块时钟信号，并且在处于待机模式时不产生这些模块时钟信号。时钟发生器还能够提供从进入关闭模式的请求到实际进入关闭模式的预定长度的延迟，从而允许时间来准备用于关闭模式的电气系统。中断旁路电路提供了在相关中断请求已被屏蔽的情况下关闭模式的方法。

3. 发明授权

US5495530A Low power emergency telephone mode 失效
标题翻译：低功率紧急电话模式
公开(公告)号：US5495530A
公开(公告)日：1996-02-27
申请号：US320778
申请日：1994-10-11
申请人： Joseph W. Peterson , Dale E. Gulick
发明人： Joseph W. Peterson , Dale E. Gulick
IPC分类号： H04B7/26 , H04M1/725 , H04M19/08 , H04M11/02
CPC分类号： H04M1/725 , H04M19/08
摘要： A cordless telephone that may be fully powered by AC main power lines and only partially powered by telephone lines includes structure for producing dual tones, structure for producing dual-tone multifrequency tones from the dual tones, and structure for empowering each of the foregoing in the event of AC main power failure where the only power available passes through the telephone lines.
摘要翻译：可以由AC主电源线完全供电并且仅部分由电话线供电的无绳电话包括用于产生双音调的结构，用于从双音调产生双音多频音调的结构，以及用于在交流主电源故障的事件，其中唯一的电力通过电话线。

4. 发明授权

US5946353A Method and apparatus for external intermediate data processing 失效
标题翻译：用于外部中间数据处理的方法和装置
公开(公告)号：US5946353A
公开(公告)日：1999-08-31
申请号：US909383
申请日：1997-08-11
申请人： Jacqueline Mullins , Joseph W. Peterson , John Bartkowiak , Alan F. Hendrickson
发明人： Jacqueline Mullins , Joseph W. Peterson , John Bartkowiak , Alan F. Hendrickson
IPC分类号： H04B14/06 , H04M1/725
CPC分类号： H04M1/725
摘要： Disclosed is a system for selectively enabling intermediate data processing of digital signals external to an integrated circuit (IC). The system comprises a transcoder, a codec connected to the transcoder, and a data processor located externally to the IC. In response to a strobe signal, a programmable switch diverts digital signals between the transcoder and the codec to a data path from the IC to the external processor. The digital signals are formatted within the IC for processing by the external processor. The externally processed digital signals are returned to the IC via a data path from the external processor. The digital signals are then reformatted within the IC for further processing by the IC.
摘要翻译：公开了一种用于选择性地实现集成电路（IC）外部的数字信号的中间数据处理的系统。该系统包括代码转换器，连接到代码转换器的编解码器和位于IC外部的数据处理器。响应于选通信号，可编程开关将代码转换器和编解码器之间的数字信号转移到从IC到外部处理器的数据路径。数字信号在IC内格式化，由外部处理器进行处理。经外部处理的数字信号通过外部处理器的数据路径返回到IC。数字信号然后在IC内重新格式化，以便IC进一步处理。

5. 发明授权

US5638405A Dual-mode baseband controller for radio-frequency interfaces relating to digital cordless telephones 失效
标题翻译：用于与数字无绳电话有关的射频接口的双模式基带控制器
公开(公告)号：US5638405A
公开(公告)日：1997-06-10
申请号：US192046
申请日：1994-02-04
申请人： Alan F. Hendrickson , Joseph W. Peterson
发明人： Alan F. Hendrickson , Joseph W. Peterson
IPC分类号： H04B1/40 , H04L27/12 , H04L27/20 , H04L27/26 , H04M1/00 , H04M1/725 , H04L27/04
CPC分类号： H04L27/12 , H04L27/2017 , H04M1/72502
摘要： A dual-mode baseband controller enables a single integrated circuit to support either In-Phase Quadrature (I-Q) or Non-Return to Zero (NRZ) radio-frequency transmitter architectures for use in second generation (CT2) cordless telephones. A radio frequency (RF) interface circuit controls output signals to support either the I-Q architecture or the NRZ architecture, depending on a MODE control bit received from a controlling integrated circuit. The RF interface circuit comprises an I-Q waveform generator, four multiplexers, two digital-to-analog converters, a buffer, interconnecting circuitry, and a timing controller operating under configurable software control.
摘要翻译：双模式基带控制器使单个集成电路能够支持用于第二代（CT2）无绳电话的同相正交（I-Q）或非归零（NRZ）射频发射机架构。根据从控制集成电路接收的MODE控制位，射频（RF）接口电路控制输出信号以支持I-Q架构或NRZ架构。 RF接口电路包括I-Q波形发生器，四个多路复用器，两个数模转换器，缓冲器，互连电路和在可配置的软件控制下操作的定时控制器。

6. 发明授权

US5657351A Method and apparatus for external intermediate data processing 失效
标题翻译：用于外部中间数据处理的方法和装置
公开(公告)号：US5657351A
公开(公告)日：1997-08-12
申请号：US668600
申请日：1996-06-19
申请人： Jacqueline Mullins , Joseph W. Peterson , John Bartkowiak , Alan F. Hendrickson
发明人： Jacqueline Mullins , Joseph W. Peterson , John Bartkowiak , Alan F. Hendrickson
IPC分类号： H04B14/06 , H04M1/725 , H04B14/08
CPC分类号： H04M1/725
摘要： Disclosed is a system for selectively enabling intermediate data processing of digital signals external to an integrated circuit (IC). The system comprises a transcoder, a codec connected to the transcoder, and a data processor located externally to the IC. In response to a strobe signal, a programmable switch diverts digital signals between the transcoder and the codec to a data path from the IC to the external processor. The digital signals are formatted within the IC for processing by the external processor. The externally processed digital signals are returned to the IC via a data path from the external processor. The digital signals are then reformatted within the IC for further processing by the IC.
摘要翻译：公开了一种用于选择性地实现集成电路（IC）外部的数字信号的中间数据处理的系统。该系统包括代码转换器，连接到代码转换器的编解码器和位于IC外部的数据处理器。响应于选通信号，可编程开关将代码转换器和编解码器之间的数字信号转换为从IC到外部处理器的数据路径。数字信号在IC内格式化，由外部处理器进行处理。经外部处理的数字信号通过外部处理器的数据路径返回到IC。数字信号然后在IC内重新格式化，以便IC进一步处理。

7. 发明授权

US5839061A Receiver quality measurement system for use in digital cordless telephones and like apparatus 失效
标题翻译：用于数字无绳电话和类似设备的接收机质量测量系统
公开(公告)号：US5839061A
公开(公告)日：1998-11-17
申请号：US531049
申请日：1995-09-20
申请人： Alan F. Hendrickson , Joseph W. Peterson
发明人： Alan F. Hendrickson , Joseph W. Peterson
IPC分类号： H04B1/10 , H04B7/08 , H04B17/00
CPC分类号： H04B1/1027 , H04B17/318 , H04B7/08
摘要： A communication circuit designed to be coupled to a radio receiver so as to receive a data signal and a receive signal strength indicator signal indicative of radio carrier strength therefrom, and further designed to be coupled to a controller, the communications circuit including a first, second, third, and fourth subcircuit. The first subcircuit receives the receive signal strength indicator from the receiver, determines radio carrier strength therefrom, and transfers the determined strength information to the controller. The second subcircuit receives the data signal from the receiver, determines if there are bit error within that signal, and transfers its determinations to the controller. The third subcircuit receives the data signal from the receiver, determines if there is jitter therein, and transfers its determinations to the controller. The fourth subcircuit is coupled to the second and third subcircuits to receive the output thereof, and is further coupled to the controller so as to receive output therefrom, the fourth subcircuit acting in response to the outputs to suppress signal noise.
摘要翻译：一种通信电路，被设计为耦合到无线电接收机，以便从其接收指示无线电载波强度的数据信号和接收信号强度指示符信号，并进一步设计为耦合到控制器，所述通信电路包括第一，第二，第三和第四分支电路。第一子电路从接收器接收接收信号强度指示符，从其确定无线电载波强度，并将确定的强度信息传送到控制器。第二分支电路接收来自接收机的数据信号，确定该信号内是否存在位错误，并将其确定传送给控制器。第三分支电路接收来自接收机的数据信号，确定其中是否存在抖动，并将其确定传送给控制器。第四子电路耦合到第二和第三子电路以接收其输出，并且还耦合到控制器，以便从其接收输出，第四子电路响应于输出而起作用以抑制信号噪声。

8. 发明授权

US5596724A Input/output data port with a parallel and serial interface 失效
标题翻译：具有并行和串行接口的输入/输出数据端口
公开(公告)号：US5596724A
公开(公告)日：1997-01-21
申请号：US191948
申请日：1994-02-04
申请人： Jacqueline Mullins , Joseph W. Peterson , John Bartkowiak , Alan F. Hendrickson
发明人： Jacqueline Mullins , Joseph W. Peterson , John Bartkowiak , Alan F. Hendrickson
IPC分类号： G06F13/38 , G06F5/00 , H03M9/00
CPC分类号： H03M9/00
摘要： The present invention disclosed an input/output data port circuit which connects a parallel data bus with an input serial data bus and an output serial data bus. The input/output data port is selectively operable in either a linear mode or a buffered mode. The input/output port is comprised of an interface register that is connected to a parallel data bus, a serial input bus and a serial output bus; a temporary register that is serially connected to the interface register, an outbound register that is connected in parallel to the temporary register and serially connected to a serial bus; and an inbound register that is connected in parallel to the temporary register and serially connected to a serial, bus.
摘要翻译：本发明公开了一种将并行数据总线与输入串行数据总线和输出串行数据总线连接的输入/输出数据端口电路。输入/输出数据端口可选择性地以线性模式或缓冲模式工作。输入/输出端口包括连接到并行数据总线，串行输入总线和串行输出总线的接口寄存器; 串行连接到接口寄存器的临时寄存器，与临时寄存器并联并串行连接到串行总线的出站寄存器; 以及与临时寄存器并行连接并串行连接到串行总线的入站寄存器。

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