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31. 发明授权

US06970024B1 Over-voltage protection of integrated circuit I/O pins 失效
标题翻译：集成电路I / O引脚的过电压保护
公开(公告)号：US06970024B1
公开(公告)日：2005-11-29
申请号：US10786370
申请日：2004-02-24
申请人： Dirk Reese , Tzung-Chin Chang , Chiakang Sung , Khai Nguyen , Gopinath Rangan , Xiaobao Wang
发明人： Dirk Reese , Tzung-Chin Chang , Chiakang Sung , Khai Nguyen , Gopinath Rangan , Xiaobao Wang
IPC分类号： H03K3/01 , H03K3/356 , H03K19/003
CPC分类号： H03K3/356113 , H03K19/00315
摘要： Circuits, methods, and apparatus for protecting devices in an output stage from over-voltage conditions caused by high supply and input voltages. Embodiments provide over-voltage protection that operates over a range of voltage levels, and that can be optimized for performance at different voltage levels. An exemplary embodiment of the present invention uses stacked devices to protect n and p-channel output devices from excess supply and input voltages. These stacked devices are biased by voltages received at their gates. These gate voltages vary as a function of supply voltage to maintain performance. Other embodiments of the present invention provide a body bias switch that generates a bias for the bulk of p-channel output devices. This bias tracks the higher of a supply or input voltage, such that parasitic drain-to-bulk diodes do not conduct. A switch may be provided that shorts the bulk connection to VCC under appropriate conditions.
摘要翻译：用于保护输出级的器件免受由高电源和输入电压引起的过电压状态的电路，方法和装置。实施例提供了在一定范围的电压电平上工作的过电压保护，并且可针对不同电压电平下的性能进行优化。本发明的示例性实施例使用堆叠器件来保护n和p沟道输出器件免受过多的电源和输入电压的影响。这些堆叠的器件被其栅极处接收的电压偏置。这些栅极电压随着电源电压而变化，以保持性能。本发明的其它实施例提供一种主体偏置开关，其产生用于大量p沟道输出装置的偏置。该偏置跟踪电源或输入电压的较高，使得寄生漏极 - 体二极管不导通。可以提供在适当条件下短路与VCC的大容量连接的开关。

32. 发明授权

US06853215B1 Programmable I/O element circuit for high speed logic devices 失效
标题翻译：用于高速逻辑器件的可编程I / O元件电路
公开(公告)号：US06853215B1
公开(公告)日：2005-02-08
申请号：US10685355
申请日：2003-10-09
申请人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Phillip Pan , In Whan Kim , Gopi Rangan , Yan Chong , Xiaobao Wang , Tzung-Chin Chang
发明人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Phillip Pan , In Whan Kim , Gopi Rangan , Yan Chong , Xiaobao Wang , Tzung-Chin Chang
IPC分类号： C07K14/47 , C07K16/28 , H03K19/173
CPC分类号： C07K16/28 , A61K2039/505 , C07K14/47
摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed 110 modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.
摘要翻译：用于逻辑阵列的I / O端子的可编程I / O元件适用于根据高速110模式（例如双数据速率和零总线周转）进行操作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块向输出缓冲器的选通输入提供使能信号。可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

33. 发明授权

US06766505B1 Parallel programming of programmable logic using register chains 有权
标题翻译：使用寄存器链的可编程逻辑的并行编程
公开(公告)号：US06766505B1
公开(公告)日：2004-07-20
申请号：US10106675
申请日：2002-03-25
申请人： Gopi Rangan , Khai Nguyen , Chiakang Sung , Xiaobao Wang , In Whan Kim , Yan Chong , Philip Pan , Joseph Huang , Bonnie Wang
发明人： Gopi Rangan , Khai Nguyen , Chiakang Sung , Xiaobao Wang , In Whan Kim , Yan Chong , Philip Pan , Joseph Huang , Bonnie Wang
IPC分类号： G06F1750
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/17764 , Y02T10/82
摘要： Techniques and circuitry are used to more rapidly configuring programmable integrated circuits. Configuration data is input into a programmable integrated circuit in parallel via parallel inputs (705), and this data is also handled internally in parallel. The configuration data will be stored in a data register (722). This data register includes two or more serial register chains, each chain being made up of a serial chain of registers. The configuration data is input into the two of more chains of the data registers in parallel. Circuitry is also provided to handle redundancy.
摘要翻译：技术和电路用于更快速地配置可编程集成电路。配置数据通过并行输入（705）并行输入到可编程集成电路中，并且该数据也在内部并行处理。配置数据将被存储在数据寄存器（722）中。该数据寄存器包括两个或多个串行寄存器链，每个链由串行寄存器组成。配置数据并行输入数据寄存器的两个链中。还提供电路来处理冗余。

34. 发明授权

US06707399B1 Data realignment techniques for serial-to-parallel conversion 有权
标题翻译：用于串行到并行转换的数据重新对准技术
公开(公告)号：US06707399B1
公开(公告)日：2004-03-16
申请号：US10269370
申请日：2002-10-10
申请人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Gopi Rangan , Nitin Prasad
发明人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Gopi Rangan , Nitin Prasad
IPC分类号： H03M900
CPC分类号： H03M9/00
摘要： Techniques for adjusting the boundary between bytes of data in a serial-to-parallel converter are provided. Bits of serial data are shifted into a first register. Data bytes are then shifted out of the first register along parallel signal lines into a second register. The timing of the parallel load of data from the first register to the second register determines the parallel data byte boundary. The boundary between the parallel data bytes can be shifted using a load enable signal. The phase of the load enable signal can be changed to shift the boundary between data bytes by one or more bits. The parallel data can then be loaded from the second register into a third register. The data output signal of the third register is synchronized to a core clock signal to ensure enough set up and hold time for signals output by the third register.
摘要翻译：提供了用于调整串并转换器中的数据字节之间边界的技术。串行数据的位被移入第一寄存器。然后，数据字节沿并行信号线移出第一寄存器，进入第二寄存器。从第一寄存器到第二寄存器的并行加载数据的时序确定并行数据字节边界。可以使用负载使能信号来移位并行数据字节之间的边界。可以改变负载使能信号的相位，以将数据字节之间的边界移位一个或多个位。然后可以将并行数据从第二寄存器加载到第三寄存器中。第三寄存器的数据输出信号与核心时钟信号同步，以确保第三寄存器输出的信号的足够的建立和保持时间。

35. 发明授权

US06400598B1 Programmable logic integrated circuit devices with low voltage differential signaling capabilities 有权
标题翻译：具有低电压差分信号功能的可编程逻辑集成电路器件
公开(公告)号：US06400598B1
公开(公告)日：2002-06-04
申请号：US09843299
申请日：2001-04-25
申请人： Khai Nguyen , Xiaobao Wang , In Whan Kim , Chiakang Sung , Richard G. Cliff , Joseph Huang , Bonnie I. Wang , Wayne Yeung
发明人： Khai Nguyen , Xiaobao Wang , In Whan Kim , Chiakang Sung , Richard G. Cliff , Joseph Huang , Bonnie I. Wang , Wayne Yeung
IPC分类号： G11C506
CPC分类号： H03K19/17744 , H03K19/018521 , H03K19/1778 , H03K19/17784
摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.
摘要翻译：可编程逻辑器件通过在器件上提供LVDS输入缓冲器和/或LVDS输出缓冲器来配备低电压差分信号（“LVDS”）。对于LVDS成对使用的设备上的I / O引脚可以单独用于其他类型的信令。尽管由于温度，制造过程不一致以及电源变化而导致变化，LVDS缓冲器也可以提供良好的性能和满足LVDS规范。

36. 发明授权

US06346827B1 Programmable logic device input/output circuit configurable as reference voltage input circuit 有权
标题翻译：可编程逻辑器件输入/输出电路可配置为参考电压输入电路
公开(公告)号：US06346827B1
公开(公告)日：2002-02-12
申请号：US09366937
申请日：1999-08-04
申请人： Wayne Yeung , Chiakang Sung , Myron W. Wong , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang , Joseph Huang , In Whan Kim
发明人： Wayne Yeung , Chiakang Sung , Myron W. Wong , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang , Joseph Huang , In Whan Kim
IPC分类号： H01L2500
CPC分类号： G11C5/147 , G11C5/066
摘要： A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.
摘要翻译：可编程逻辑器件输入/输出引脚的可编程输入/输出电路可以在标准I / O模式或参考电压模式下进行配置。该电路包括可跟踪的标准I / O缓冲器以及参考电压钳位电路。在参考电压模式下，I / O电路被三态化，参考电压钳位电路将参考电压从I / O引脚传递到参考电压总线。在标准I / O模式下，I / O缓冲区可以运行。参考电压钳位电路将I / O引脚与参考电压总线隔离，并可能包括欠压和过压保护，以防止参考电压总线受到超出范围I / O信号的干扰。

37. 发明授权

US08610462B1 Input-output circuit and method of improving input-output signals 有权
标题翻译：输入输出电路及改善输入输出信号的方法
公开(公告)号：US08610462B1
公开(公告)日：2013-12-17
申请号：US13332730
申请日：2011-12-21
申请人： Xiaobao Wang , Chiakang Sung , Khai Nguyen , Bonnie I. Wang
发明人： Xiaobao Wang , Chiakang Sung , Khai Nguyen , Bonnie I. Wang
IPC分类号： H03K19/094 , H03K19/0175 , H03K3/00 , H03B1/00
CPC分类号： H03K3/356113
摘要： Circuits and techniques for operating an integrated circuit (IC) with a level shifter circuit are disclosed. A level shifter circuit with input and output terminals is operable to shift an input signal that ranges from a ground voltage to a first positive voltage to an output signal that ranges from the ground voltage to a second positive voltage. The level shifter circuit further includes a first kicker transistor having a first source-drain terminal operable to receive a buffered version of the input signal and having a second source-drain terminal coupled to the output terminal. The first kicker transistor may receive gate signals that turn on the first kicker transistor when the input signal is at the ground voltage and may pull the output terminal to the first positive voltage as the input signal transitions from the ground voltage to the first positive voltage.
摘要翻译：公开了用于利用电平移位器电路来操作集成电路（IC）的电路和技术。具有输入和输出端子的电平移位器电路可操作以将从地电压到第一正电压的输入信号移动到范围从接地电压到第二正电压的输出信号。电平移位器电路还包括具有第一源极 - 漏极端子的第一汲取晶体管，第一源极 - 漏极端子可操作以接收缓冲版本的输入信号并具有耦合到输出端子的第二源极 - 漏极端子。当输入信号处于接地电压时，第一icker晶体晶体管可以接收导通第一猝发晶体管的栅极信号，并且当输入信号从接地电压转变到第一正电压时，可以将输出端拉至第一正电压。

38. 发明授权

US08390315B1 Configurable input-output (I/O) circuitry with pre-emphasis circuitry 有权
标题翻译：具有预加重电路的可组态输入输出（I / O）电路
公开(公告)号：US08390315B1
公开(公告)日：2013-03-05
申请号：US13354780
申请日：2012-01-20
申请人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Khai Nguyen
发明人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Khai Nguyen
IPC分类号： H03K19/013 , H03K17/16
CPC分类号： H03K19/01721 , H03K19/018571
摘要： Circuits and techniques for operating an integrated circuit (IC) with a configurable input-output circuit are disclosed. A disclosed circuit includes a single-ended input-output buffer coupled to an output terminal. The single-ended input-output buffer is operable to transmit an input signal to the output terminal as an output signal. A pre-emphasis circuit that is operable to sharpen a first edge and a second edge of the output signal is coupled between the single-ended input-output buffer and the output terminal. The first edge of the output signal is sharpened when the input signal switches from a first logic level to a second logic level while the second edge of the output signal is sharpened when the input signal switches from the second logic level to the first logic level.
摘要翻译：公开了具有可配置的输入 - 输出电路来操作集成电路（IC）的电路和技术。所公开的电路包括耦合到输出端子的单端输入 - 输出缓冲器。单端输入 - 输出缓冲器可用于将输入信号作为输出信号发送到输出端。用于锐化输出信号的第一边缘和第二边缘的预加重电路耦合在单端输入 - 输出缓冲器和输出端子之间。当输入信号从第一逻辑电平切换到第二逻辑电平时，输出信号的第一边缘被锐化，而当输入信号从第二逻辑电平切换到第一逻辑电平时，输出信号的第二边沿被锐化。

39. 发明授权

US07994821B1 Level shifter circuits and methods 有权
标题翻译：电平移位电路和方法
公开(公告)号：US07994821B1
公开(公告)日：2011-08-09
申请号：US12753389
申请日：2010-04-02
申请人： Xiaobao Wang , Chiakang Sung , Khai Nguyen
发明人： Xiaobao Wang , Chiakang Sung , Khai Nguyen
IPC分类号： H03K19/0175
CPC分类号： H03K3/356069
摘要： A level shifter circuit includes first and second transistors coupled in series and third and fourth transistors coupled in series. The fourth transistor is coupled to a first node between the first and the second transistors. The level shifter circuit also includes fifth and sixth transistors coupled in series and seventh and eighth transistors coupled in series. The eighth transistor is coupled to a second node between the fifth and the sixth transistors. The second and the eighth transistors receive a first input signal at control inputs. The fourth and the sixth transistors receive a second input signal at control inputs. The second input signal is inverted relative to the first input signal.
摘要翻译：电平移位器电路包括串联耦合的第一和第二晶体管，以及串联耦合的第三和第四晶体管。第四晶体管耦合到第一和第二晶体管之间的第一节点。电平移位器电路还包括串联耦合的第五和第六晶体管，以及串联耦合的第七和第八晶体管。第八晶体管耦合到第五和第六晶体管之间的第二节点。第二和第八晶体管在控制输入端接收第一输入信号。第四和第六晶体管在控制输入端接收第二输入信号。第二输入信号相对于第一输入信号反相。

40. 发明授权

US07973553B1 Techniques for on-chip termination 有权
标题翻译：片上终止技术
公开(公告)号：US07973553B1
公开(公告)日：2011-07-05
申请号：US12721759
申请日：2010-03-11
申请人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen , John Henry Bui
发明人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen , John Henry Bui
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0278
摘要： A circuit includes first transistors and a comparator. The comparator compares a reference signal and a signal that is based on conductive states of the first transistors. A control circuit generates first control signals based on an output signal of the comparator. The conductive states of the first transistors are determined based on the first control signals. An arithmetic circuit performs an arithmetic function based on the first control signals and second control signals to generate calibration signals. Second transistors provide a termination impedance at an external terminal of the circuit that is based on the calibration signals.
摘要翻译：电路包括第一晶体管和比较器。比较器比较参考信号和基于第一晶体管的导电状态的信号。控制电路根据比较器的输出信号产生第一控制信号。基于第一控制信号来确定第一晶体管的导通状态。算术电路基于第一控制信号和第二控制信号执行运算功能，以生成校准信号。第二晶体管在基于校准信号的电路的外部端子处提供终端阻抗。

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