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1. 发明授权

US06766505B1 Parallel programming of programmable logic using register chains 有权
标题翻译：使用寄存器链的可编程逻辑的并行编程
公开(公告)号：US06766505B1
公开(公告)日：2004-07-20
申请号：US10106675
申请日：2002-03-25
申请人： Gopi Rangan , Khai Nguyen , Chiakang Sung , Xiaobao Wang , In Whan Kim , Yan Chong , Philip Pan , Joseph Huang , Bonnie Wang
发明人： Gopi Rangan , Khai Nguyen , Chiakang Sung , Xiaobao Wang , In Whan Kim , Yan Chong , Philip Pan , Joseph Huang , Bonnie Wang
IPC分类号： G06F1750
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/17764 , Y02T10/82
摘要： Techniques and circuitry are used to more rapidly configuring programmable integrated circuits. Configuration data is input into a programmable integrated circuit in parallel via parallel inputs (705), and this data is also handled internally in parallel. The configuration data will be stored in a data register (722). This data register includes two or more serial register chains, each chain being made up of a serial chain of registers. The configuration data is input into the two of more chains of the data registers in parallel. Circuitry is also provided to handle redundancy.
摘要翻译：技术和电路用于更快速地配置可编程集成电路。配置数据通过并行输入（705）并行输入到可编程集成电路中，并且该数据也在内部并行处理。配置数据将被存储在数据寄存器（722）中。该数据寄存器包括两个或多个串行寄存器链，每个链由串行寄存器组成。配置数据并行输入数据寄存器的两个链中。还提供电路来处理冗余。

2. 发明授权

US06870400B1 Supply voltage detection circuit 有权
标题翻译：电源电压检测电路
公开(公告)号：US06870400B1
公开(公告)日：2005-03-22
申请号：US10678498
申请日：2003-10-03
申请人： Yan Chong , Chiakang Sung , Bonnie Wang , Khai Nguyen , Joseph Huang , Xiaobao Wang , Philip Pan , In Whan Kim , Gopi Rangan , Tzung-Chin Chang , Surgey Y. Shumarayev , Thomas H. White
发明人： Yan Chong , Chiakang Sung , Bonnie Wang , Khai Nguyen , Joseph Huang , Xiaobao Wang , Philip Pan , In Whan Kim , Gopi Rangan , Tzung-Chin Chang , Surgey Y. Shumarayev , Thomas H. White
IPC分类号： G01R19/155 , G06F1/24 , G06F1/28 , G06F1/32 , H03K3/356 , H03K17/22 , H03K19/0175
CPC分类号： H03K3/356008 , G01R19/155 , G06F1/24 , G06F1/28 , G06F1/3203 , H03K17/223
摘要： A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal levels, including low supply signal levels, while limiting leakage current effects.
摘要翻译：电源电压检测电路确定由集成电路装置接收的任何一个电源信号的电压何时低于其稳定状态电平，这可能是在插座状态期间可能发生的，在系统上。第一检测电路确定第一电源电压何时低于其稳态电平，第二检测电路确定第二电源电压何时低于其稳态电平。逻辑电路提供检测条件信号，其禁止通过与电源电压检测电路相关联的输入/输出端子的电流流动。该电路能够快速检测广泛范围的电源信号电平（包括低电源信号电平）的热插座状况，同时限制漏电流效应。

3. 发明授权

US06630844B1 Supply voltage detection circuit 有权
标题翻译：电源电压检测电路
公开(公告)号：US06630844B1
公开(公告)日：2003-10-07
申请号：US09887686
申请日：2001-08-22
申请人： Yan Chong , Chiakang Sung , Bonnie Wang , Khai Nguyen , Joseph Huang , Xiaobao Wang , Philip Pan , In Whan Kim , Gopi Rangan , Tzung-Chin Chang , Surgey Y. Shumarayev , Thomas H. White
发明人： Yan Chong , Chiakang Sung , Bonnie Wang , Khai Nguyen , Joseph Huang , Xiaobao Wang , Philip Pan , In Whan Kim , Gopi Rangan , Tzung-Chin Chang , Surgey Y. Shumarayev , Thomas H. White
IPC分类号： H03K190175
CPC分类号： H03K3/356008 , G01R19/155 , G06F1/24 , G06F1/28 , G06F1/3203 , H03K17/223
摘要： A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal; levels, including low supply signal levels, while limiting leakage current effects.
摘要翻译：电源电压检测电路确定由集成电路装置接收的任何一个电源信号的电压何时低于其稳定状态电平，这可能是在插座状态期间可能发生的，在系统上。第一检测电路确定第一电源电压何时低于其稳态电平，第二检测电路确定第二电源电压何时低于其稳态电平。逻辑电路提供检测条件信号，其禁止通过与电源电压检测电路相关联的输入/输出端子的电流流动。该电路能够快速检测广泛的电源信号的热插座状况; 电平，包括低电平信号电平，同时限制漏电流效应。

4. 发明授权

US07119579B2 Supply voltage detection circuit 有权
标题翻译：电源电压检测电路
公开(公告)号：US07119579B2
公开(公告)日：2006-10-10
申请号：US11005890
申请日：2004-12-06
申请人： Yan Chong , Chiakang Sung , Bonnie Wang , Khai Nguyen , Joseph Huang , Xiaobao Wang , Philip Pan , In Whan Kim , Gopi Rangan , Tzung-Chin Chang , Surgey Y. Shumarayev , Thomas H. White
发明人： Yan Chong , Chiakang Sung , Bonnie Wang , Khai Nguyen , Joseph Huang , Xiaobao Wang , Philip Pan , In Whan Kim , Gopi Rangan , Tzung-Chin Chang , Surgey Y. Shumarayev , Thomas H. White
IPC分类号： H03K19/0175
CPC分类号： H03K3/356008 , G01R19/155 , G06F1/24 , G06F1/28 , G06F1/3203 , H03K17/223
摘要： A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal levels, including low supply signal levels, while limiting leakage current effects.
摘要翻译：电源电压检测电路确定由集成电路装置接收的任何一个电源信号的电压何时低于其稳定状态电平，这可能是在插座状态期间可能发生的，在系统上。第一检测电路确定第一电源电压何时低于其稳态电平，第二检测电路确定第二电源电压何时低于其稳态电平。逻辑电路提供检测条件信号，其禁止通过与电源电压检测电路相关联的输入/输出端子的电流流动。该电路能够快速检测广泛范围的电源信号电平（包括低电源信号电平）的热插座状况，同时限制漏电流效应。

5. 发明授权

US06714044B1 Hi-speed parallel configuration of programmable logic 有权
标题翻译：高速并行配置可编程逻辑
公开(公告)号：US06714044B1
公开(公告)日：2004-03-30
申请号：US10106673
申请日：2002-03-25
申请人： Gopi Rangan , Khai Nguyen , Chiakang Sung , Xiaobao Wang , In Whan Kim , Yan Chong , Philip Pan , Joseph Huang , Bonnie Wang
发明人： Gopi Rangan , Khai Nguyen , Chiakang Sung , Xiaobao Wang , In Whan Kim , Yan Chong , Philip Pan , Joseph Huang , Bonnie Wang
IPC分类号： G06F738
CPC分类号： H03K19/17776 , G11C2207/104 , H03K19/17764
摘要： Techniques and circuitry are used to more rapidly configuring programmable integrated circuits. Configuration data is input into a programmable integrated circuit in parallel via parallel inputs (705), and this data is also handled internally in parallel. The configuration data will be stored in a data register (722). This data register is segmented into two or more segments, each segment being made up of a serial chain of registers (808). The configuration data is input into the two of more segments of the data registers in parallel. Circuitry is also provided to handle redundancy.
摘要翻译：技术和电路用于更快速地配置可编程集成电路。配置数据通过并行输入（705）并行输入到可编程集成电路中，并且该数据也在内部并行处理。配置数据将被存储在数据寄存器（722）中。该数据寄存器被分割成两个或多个段，每个段由串行链路寄存器（808）组成。配置数据并行输入数据寄存器的两个更多段。还提供电路来处理冗余。

6. 发明授权

US06731142B1 Circuit for providing clock signals with low skew 有权
标题翻译：提供低偏移时钟信号的电路
公开(公告)号：US06731142B1
公开(公告)日：2004-05-04
申请号：US10412705
申请日：2003-04-10
申请人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopi Rangan , Yan Chong , Phillip Pan , Tzung-Chin Chang
发明人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopi Rangan , Yan Chong , Phillip Pan , Tzung-Chin Chang
IPC分类号： H03K2100
CPC分类号： H03M9/00 , G06F1/08 , H03K5/135
摘要： A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.
摘要翻译：公开了一种数字，优选可编程的电路，用于提供具有可变频率和/或相位的一个或多个时钟信号。时钟信号相对于由该电路提供的其它时钟信号和数据信号呈现低的偏移量。在一个实施例中，电路包括多个通道，每个通道具有并行/串行输出移位寄存器，触发器和延迟电路。移位寄存器可以在分频时钟通道中的数据通道或时钟频率选择位中接收数据位。来自寄存器的串行输出用作触发器的输入，两者均由输入参考时钟触发。延迟电路延迟输入参考时钟。在每个通道中，多路复用器被配置为选择从寄存器，触发器和延迟电路输出输出的时钟或数据通道。由于所有输出路径中的延迟相匹配，所以偏斜最小化。

7. 发明授权

US06549045B1 Circuit for providing clock signals with low skew 有权
标题翻译：提供低偏移时钟信号的电路
公开(公告)号：US06549045B1
公开(公告)日：2003-04-15
申请号：US10043620
申请日：2002-01-11
申请人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopi Rangan , Yan Chong , Phillip Pan , Tzung-Chin Chang
发明人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopi Rangan , Yan Chong , Phillip Pan , Tzung-Chin Chang
IPC分类号： H03K2100
CPC分类号： H03M9/00 , G06F1/08 , H03K5/135
摘要： A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.
摘要翻译：公开了一种数字，优选可编程的电路，用于提供具有可变频率和/或相位的一个或多个时钟信号。时钟信号相对于由该电路提供的其它时钟信号和数据信号呈现低的偏移量。在一个实施例中，电路包括多个通道，每个通道具有并行/串行输出移位寄存器，触发器和延迟电路。移位寄存器可以在分频时钟通道中的数据通道或时钟频率选择位中接收数据位。来自寄存器的串行输出用作触发器的输入，两者均由输入参考时钟触发。延迟电路延迟输入参考时钟。在每个通道中，多路复用器被配置为选择从寄存器，触发器和延迟电路输出输出的时钟或数据通道。由于所有输出路径中的延迟相匹配，所以偏斜最小化。

8. 发明授权

US06853215B1 Programmable I/O element circuit for high speed logic devices 失效
标题翻译：用于高速逻辑器件的可编程I / O元件电路
公开(公告)号：US06853215B1
公开(公告)日：2005-02-08
申请号：US10685355
申请日：2003-10-09
申请人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Phillip Pan , In Whan Kim , Gopi Rangan , Yan Chong , Xiaobao Wang , Tzung-Chin Chang
发明人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Phillip Pan , In Whan Kim , Gopi Rangan , Yan Chong , Xiaobao Wang , Tzung-Chin Chang
IPC分类号： C07K14/47 , C07K16/28 , H03K19/173
CPC分类号： C07K16/28 , A61K2039/505 , C07K14/47
摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed 110 modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.
摘要翻译：用于逻辑阵列的I / O端子的可编程I / O元件适用于根据高速110模式（例如双数据速率和零总线周转）进行操作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块向输出缓冲器的选通输入提供使能信号。可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

9. 发明申请

US20050162187A1 Programmable I/O element circuit for high speed logic devices 有权
标题翻译：用于高速逻辑器件的可编程I / O元件电路
公开(公告)号：US20050162187A1
公开(公告)日：2005-07-28
申请号：US11025774
申请日：2004-12-29
申请人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Phillip Pan , In Whan Kim , Gopi Rangan , Yan Chong , Xiaobao Wang , Tzung-Chin Chang
发明人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Phillip Pan , In Whan Kim , Gopi Rangan , Yan Chong , Xiaobao Wang , Tzung-Chin Chang
IPC分类号： C07K14/47 , C07K16/28 , H03K19/177
CPC分类号： C07K16/28 , A61K2039/505 , C07K14/47
摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.
摘要翻译：用于逻辑阵列的I / O端子的可编程I / O元件适用于根据双速数据速率和零总线周转等高速I / O模式进行工作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块为输出缓冲器的选通输入提供使能信号。可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

10. 发明授权

US06686769B1 Programmable I/O element circuit for high speed logic devices 有权
标题翻译：用于高速逻辑器件的可编程I / O元件电路
公开(公告)号：US06686769B1
公开(公告)日：2004-02-03
申请号：US10017666
申请日：2001-12-14
申请人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Phillip Pan , In Whan Kim , Gopi Rangan , Yan Chong , Xiaobao Wang , Tzung-Chin Chang
发明人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Phillip Pan , In Whan Kim , Gopi Rangan , Yan Chong , Xiaobao Wang , Tzung-Chin Chang
IPC分类号： H03K19173
CPC分类号： C07K16/28 , A61K2039/505 , C07K14/47
摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.
摘要翻译：用于逻辑阵列的I / O端子的可编程I / O元件适用于根据高速I / O模式（如双数据速率和零总线周转）进行工作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块向输出缓冲器的选通输入提供使能信号。可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

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