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31. 发明申请

US20070147564A1 Phase interpolator 有权
标题翻译：相位插值器
公开(公告)号：US20070147564A1
公开(公告)日：2007-06-28
申请号：US11319879
申请日：2005-12-27
申请人： Yongping Fan , Ian Young
发明人： Yongping Fan , Ian Young
IPC分类号： H04L7/00 , H04L7/04 , H03H11/16
CPC分类号： H03H11/16 , H04L7/0338
摘要： A phase interpolator includes a first circuit to generate a first signal having a first phase delay and a second signal having a second phase delay and a phase mixer. The phase mixer is coupled to receive the first and second signals from the first circuit. The phase mixer includes multiple current drivers each including a current driver input coupled to selectively delay one of the first or second signals and a current driver output coupled to output a phase delayed signal. The current driver outputs of the current drivers are coupled together to combine the phase delayed signals from the current drivers to generate an output phase delayed signal having a phase interpolated from the first and second signals.
摘要翻译：相位插值器包括产生具有第一相位延迟的第一信号和具有第二相位延迟的第二信号和相位混频器的第一电路。耦合相位混合器以接收来自第一电路的第一和第二信号。相位混合器包括多个电流驱动器，每个电流驱动器包括耦合以选择性地延迟第一或第二信号中的一个的电流驱动器输入和耦合以输出相位延迟信号的电流驱动器输出。电流驱动器的当前驱动器输出耦合在一起以组合来自电流驱动器的相位延迟信号，以产生具有从第一和第二信号内插的相位的输出相位延迟信号。

32. 发明授权

US07236920B2 Mechanism for estimating and controlling di/dt-induced power supply voltage variations 有权
标题翻译：用于估计和控制di / dt感应电源电压变化的机制
公开(公告)号：US07236920B2
公开(公告)日：2007-06-26
申请号：US11317948
申请日：2005-12-23
申请人： Edward T. Grochowski , David Sager , Vivek Tiwari , Ian Young , David J. Ayers
发明人： Edward T. Grochowski , David Sager , Vivek Tiwari , Ian Young , David J. Ayers
IPC分类号： G06F17/50
CPC分类号： G06F1/3296 , G06F1/26 , G06F1/3203 , G06F17/5036 , G06F2217/78 , Y02D10/172
摘要： A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the device. A current computation unit stores values representing a sequence of current amplitudes drawn by the device on successive clock cycles, and provides them to a current to voltage computation unit. The current to voltage computation unit filters the current amplitudes according to coefficients derived from the response function to provide an estimate of the voltage seen by the device. Operation of the device is adjusted if the estimated voltage falls outside the specified range.
摘要翻译：公开了一种用于向特定电压范围内的设备供电的系统。该系统包括功率传递网络，其特征在于响应功能，以向设备传送电力。当前计算单元存储表示在连续的时钟周期上由设备绘制的当前幅度序列的值，并将其提供给电流到电压计算单元。电流对电压计算单元根据从响应函数导出的系数对当前幅度进行滤波，以提供器件所看到的电压的估计。如果估计电压超出规定范围，则调整设备的运行。

33. 发明授权

US07035785B2 Mechanism for estimating and controlling di/dt-induced power supply voltage variations 失效
公开(公告)号：US07035785B2
公开(公告)日：2006-04-25
申请号：US10040582
申请日：2001-12-28
申请人： Edward T. Grochowski , David Sager , Vivek Tiwari , Ian Young , David J. Ayers
发明人： Edward T. Grochowski , David Sager , Vivek Tiwari , Ian Young , David J. Ayers
IPC分类号： G06F17/50
CPC分类号： G06F1/3296 , G06F1/26 , G06F1/3203 , G06F17/5036 , G06F2217/78 , Y02D10/172
摘要： A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the device. A current computation unit stores values representing a sequence of current amplitudes drawn by the device on successive clock cycles, and provides them to a current to voltage computation unit. The current to voltage computation unit filters the current amplitudes according to coefficients derived from the response function to provide an estimate of the voltage seen by the device. Operation of the device is adjusted if the estimated voltage falls outside the specified range.

34. 发明授权

US07026883B2 Feedback loop for LC VCO 有权
标题翻译： LC VCO的反馈回路
公开(公告)号：US07026883B2
公开(公告)日：2006-04-11
申请号：US10801395
申请日：2004-03-12
申请人： Harish Muthali , Ian Young , Joseph F. Ahadian
发明人： Harish Muthali , Ian Young , Joseph F. Ahadian
IPC分类号： H03B5/04
CPC分类号： H03B5/04 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B2200/0062 , H03B2200/0066
摘要： A voltage-controlled oscillator includes an inductor capacitor (LC) tank; a drive circuit having a current source; and a feedback loop circuit. The feedback loop includes a peak detect circuit to generate a peak detect voltage; a reference voltage generator to generate a single reference voltage; and an operational amplifier, coupled to the peak detect circuit and the reference voltage generator, to generate an analog bias signal to adjust a current of the current source.
摘要翻译：压控振荡器包括电感电容器（LC）箱; 具有电流源的驱动电路; 和反馈回路电路。反馈回路包括产生峰值检测电压的峰值检测电路; 参考电压发生器，用于产生单个参考电压; 以及耦合到峰值检测电路和参考电压发生器的运算放大器，以产生模拟偏置信号以调节电流源的电流。

35. 发明授权

US6064223A Low leakage circuit configuration for MOSFET circuits 失效
标题翻译： MOSFET电路的低漏电路配置
公开(公告)号：US6064223A
公开(公告)日：2000-05-16
申请号：US111450
申请日：1998-07-08
申请人： Yi Lu , Ian Young
发明人： Yi Lu , Ian Young
IPC分类号： H03K19/00 , H03K17/16
CPC分类号： H03K19/0016
摘要： A circuit configured with MOSFETs having a first range of subthreshold conduction, is provided with at least one switchable pathway between the circuit and a power or ground node, such that the switchable pathway is operable to substantially reduce leakage current through the circuit. In a further aspect of the present invention, the switchable pathway is a FET having substantially the same subthreshold conduction characteristics as the FETs in the circuit to which the switchable pathway is coupled, the FET being configured to be driven into both inversion and accumulation.
摘要翻译：配置有具有第一范围的亚阈值导通的MOSFET的电路在电路和电源或接地节点之间设置有至少一个可切换路径，使得可切换路径可操作以基本上减少通过电路的泄漏电流。在本发明的另一方面，可切换路径是具有与可切换路径耦合的电路中的FET具有基本相同的亚阈值导通特性的FET，所述FET被配置为被驱动为反相和积累。

36. 发明授权

US5412349A PLL clock generator integrated with microprocessor 失效
标题翻译： PLL时钟发生器与微处理器集成
公开(公告)号：US5412349A
公开(公告)日：1995-05-02
申请号：US861288
申请日：1992-03-31
申请人： Ian Young , Keng L. Wong , Jeffrey K. Greason
发明人： Ian Young , Keng L. Wong , Jeffrey K. Greason
IPC分类号： H03K3/0231 , H03L7/089 , H03L7/099 , H03B5/02
CPC分类号： H03L7/0995 , H03K3/0231 , H03L7/0891 , H03L2207/06
摘要： A PLL based deskewed clock generator which may be fully integrated on a microprocessor is disclosed. The clock generator has a skew of less than 0.1 ns with peak to peak jitter of 0.3 ns using a 0.8 .mu.m CMOS technology. The PLL comprises a phase frequency detector, charge pump, loop filter and voltage controlled oscillator from which the internal clock is generated. Since the PLL is on the same chip as the microprocessor, it is difficult to isolate the PLL from the noise generated by the microprocessor core logic and output buffers. Without an external filter, noise from the motherboard also influences the PLL. Power supply noise can cause a direct change in the frequency of the voltage controlled oscillator of the PLL. Circuits which overcome the adverse effects which would be created by such noises are also described.
摘要翻译：公开了一种可以完全集成在微处理器上的基于PLL的偏移时钟发生器。时钟发生器的偏移小于0.1 ns，峰值抖动为0.3 ns，采用0.8μmCMOS技术。 PLL包括相位频率检测器，电荷泵，环路滤波器和产生内部时钟的压控振荡器。由于PLL与微处理器在同一芯片上，所以难以将PLL与微处理器核心逻辑和输出缓冲器产生的噪声隔离开来。没有外部滤波器，主板噪声也会影响PLL。电源噪声可能导致PLL压控振荡器频率的直接变化。还描述了克服由这种噪声产生的不利影响的电路。

37. 发明授权

US07619452B2 Mutual charge cancelling sample-reset loop filter for phase locked loops 有权
公开(公告)号：US07619452B2
公开(公告)日：2009-11-17
申请号：US12079786
申请日：2008-03-28
申请人： Hyung-Jin Lee , Ian Young
发明人： Hyung-Jin Lee , Ian Young
IPC分类号： H03L7/06 , H03K5/00
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/18
摘要： In general, in one aspect, an apparatus includes a phase frequency detector, a charge pump, a voltage controlled oscillator, an integral capacitor to maintain an integral charge and provide an integral voltage, and a mutual-charge canceling sample reset (MCSR) capacitor to maintain a proportional charge and provide a proportional voltage each reference clock cycle. The MCSR includes a first proportional capacitor, a second proportional capacitor in parallel to, and having substantially identical capacitance value as, the first proportional capacitor, a first set of switches to provide direct coupling of the first and second proportional capacitors, and a second set of switches to provide cross coupling of the first and second proportional capacitors. The first and second set of switches alternatively turn on and off every reference clock cycle so that set of switches coupling the first and second proportional capacitors alternates every reference clock cycle.

38. 发明申请

US20080180185A1 VCO amplitude control 有权
标题翻译： VCO振幅控制
公开(公告)号：US20080180185A1
公开(公告)日：2008-07-31
申请号：US11701303
申请日：2007-01-31
申请人： Yongping Fan , Ian Young
发明人： Yongping Fan , Ian Young
IPC分类号： H03L5/00 , H03B5/12
CPC分类号： H03L5/00 , H03L7/099 , H03L2207/06
摘要： Disclosed are circuits and methods to control the amplitude of a signal generated by a VCO.
摘要翻译：公开了用于控制由VCO产生的信号的幅度的电路和方法。

39. 发明申请

US20070163413A1 Steel rule die and metal sectional counter 审中-公开
标题翻译：钢规模和金属截面计数器
公开(公告)号：US20070163413A1
公开(公告)日：2007-07-19
申请号：US11334300
申请日：2006-01-18
申请人： John Salusbury , Ian Young , John Eales
发明人： John Salusbury , Ian Young , John Eales
IPC分类号： B26D1/00
CPC分类号： B26F1/44 , B26D7/20 , B26F1/40 , B26F2001/4418 , B26F2001/4445 , B31B50/16 , B31B50/252 , B31F1/08 , Y10T83/9295 , Y10T83/9454
摘要： A multiple segment steel rule die is provided comprising a base plate having one or more channels formed therein, cutting rules secured in the channels, scoring rules secured in the channels, and at least one counter plate for cooperating with the base plate. The counter plate has slots formed therein for receiving the scoring rules. The base plate and the at least one counter plate are removably fixed to opposite heads of a press to facilitate operation of the steel rule die. The multiple segment steel rule die produces at least two blanks from stock material during a pressing operation.
摘要翻译：提供了一种多段钢规则模具，包括：一个基板，其中形成有一个或多个通道，固定在通道中的切割规则，固定在通道中的划线规则，以及用于与基板配合的至少一个计数板。计数器板具有形成在其中的槽，用于接收评分规则。基板和至少一个计数板可移除地固定到压机的相对的头部，以便于钢制模具的操作。多段钢规则模具在压制操作期间从原料生产至少两个坯料。

40. 发明申请

US20060250686A1 Optical microscope and method for obtaining an optical image 审中-公开
标题翻译：光学显微镜和获得光学图像的方法
公开(公告)号：US20060250686A1
公开(公告)日：2006-11-09
申请号：US11393523
申请日：2006-03-29
申请人： Yuval Garini , Ian Young
发明人： Yuval Garini , Ian Young
IPC分类号： G02B21/00
CPC分类号： G01Q60/22 , G02B21/0032 , G02B21/06
摘要： The invention relates to an optical microscope, comprising, at least a light source, a carrier for an object to be examined, a detector for registering the illuminated object, and a light path that during operation runs substantially from the light source to the object and form the object to the detector, wherein a metallic film having a periodic hole array is placed in the light path between the light source and the object, and wherein the carrier of the object is provided with a drive to allow the same to be adjusted in the plane of the carrier, wherein the holes of the metallic thin film have a diameter that is smaller than approximately 250 nm, in that the drive is designed for adjusting the carrier for the object in an orientation perpendicular to the plane of the carrier, and in that a processing device is provided that is connected with the detector for constructing a three-dimensional image of the object.
摘要翻译：本发明涉及一种光学显微镜，包括至少一个光源，用于待检测物体的载体，用于登记照射物体的检测器和在操作期间基本上从光源到物体运行的光路，以及形成物体到检测器，其中具有周期性孔阵列的金属膜被放置在光源和物体之间的光路中，并且其中物体的载体设置有驱动器，以允许其被调节载体的平面，其中金属薄膜的孔具有小于约250nm的直径，因为驱动器设计成用于在垂直于载体的平面的方向上调整用于物体的载体，以及因为提供了与用于构建物体的三维图像的检测器连接的处理装置。

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