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    • 31. 发明申请
    • Low noise amplifier
    • 低噪声放大器
    • US20070105523A1
    • 2007-05-10
    • US10560703
    • 2004-06-11
    • Takefumi NishimutaHiroshi MiyagiTadahiro OhmiShigetoshi SugawaAkinobu Teramoto
    • Takefumi NishimutaHiroshi MiyagiTadahiro OhmiShigetoshi SugawaAkinobu Teramoto
    • H04B1/10H04B1/28H04B1/16
    • H01L21/82385H01L21/823807H01L27/092H01L29/785H03F1/26H03F2200/372H03G1/0029H03G1/007
    • A low noise amplifier is assumed to comprise an MIS transistor and to amplify an input signal keeping noise at a low level, and the MIS transistor comprises a semiconductor substrate for comprising a first crystal plane as a principal plane, a semiconductor structure, formed as a part of the semiconductor substrate, for comprising a pair of sidewall planes defined by the second crystal plane different from the first crystal plane and a top plane defined by the third crystal plane different from the second crystal plane, a gate insulator of uniform thickness covering the principal plane, the sidewall planes and the top plane, a gate electrode for continuously covering the principal plane, the sidewall planes and the top plane on top of the gate insulator, and a single conductivity type diffusion area formed in the region to either side of the gate electrode in the semiconductor substrate and the semiconductor structure and continuously extending along the principal plane, the sidewall planes and the top plane. Such a configuration allows significant reduction of the 1/f noise and the signal distortion applied to an output signal by the low noise amplifier and therefore a circuit for compensating for the reduction of the amplitude is no longer of necessity, allowing reduction in size.
    • 假设低噪声放大器包括MIS晶体管并且将保持噪声保持在低电平的输入信号放大,并且MIS晶体管包括用于包括第一晶面作为主平面的半导体衬底,形成为 所述半导体衬底的一部分包括由不同于所述第一晶体面的所述第二晶体面限定的一对侧壁平面和由与所述第二晶体面不同的所述第三晶体面限定的顶面,覆盖所述半导体衬底的均匀厚度的栅极绝缘体 主平面,侧壁平面和顶面,用于连续覆盖主平面,侧壁平面和栅极绝缘体顶部的顶面的栅极,以及在该区域中形成的单一导电型扩散区域 半导体衬底中的栅电极和半导体结构,并且沿着主平面连续延伸,侧壁p 车道和顶层飞机。 这样的配置允许显着降低由低噪声放大器施加到输出信号的1 / f噪声和信号失真,因此不再需要用于补偿幅度减小的电路,从而允许尺寸减小。