专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07098083B2 High impedance antifuse 失效
标题翻译：高阻抗反熔丝
公开(公告)号：US07098083B2
公开(公告)日：2006-08-29
申请号：US10652534
申请日：2003-08-29
申请人： John A. Fifield , Russell J. Houghton , William R. Tonti
发明人： John A. Fifield , Russell J. Houghton , William R. Tonti
IPC分类号： H01L21/82
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , Y10S438/957 , H01L2924/00
摘要： A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.
摘要翻译：一种可编程元件，其具有第一二极管，其具有电极和设置在所述基板和所述第一器件的所述电极之间的第一绝缘体，所述第一绝缘体具有给定特性的第一值，以及设置有电极和第二绝缘体的FET 在所述基板和所述第二装置的所述电极之间，所述第二绝缘体具有与所述第一值不同的所述给定特性的第二值。二极管和FET的电极彼此耦合，并且编程能量源耦合到二极管，以使其在编程时永久地降低电阻率。二极管的编程状态由FET中的电流表示，该电流由读出锁存器读取。因此，二极管中的小电阻变化转换为锁存器中的大信号增益/变化。这允许二极管在较低的电压下被编程。

32. 发明授权

US06631503B2 Temperature programmable timing delay system 失效
公开(公告)号：US06631503B2
公开(公告)日：2003-10-07
申请号：US09755860
申请日：2001-01-05
申请人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield
发明人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield
IPC分类号： G06F1750
CPC分类号： G06F1/206 , H03K2005/00143 , Y02D10/16
摘要： The present invention provides a temperature programmable timing delay system utilizing circuitry for generating a band-gap reference and for sensing the on-chip temperature of an integrated circuit chip. The circuitry outputs the sensed temperature as a binary output which is received by a programmable table circuit of the timing delay system. The programmable table circuit outputs a binary output corresponding to the received binary output. The timing delay system further includes a temperature dependent timing delay circuit having inputs for receiving the binary output of the programmable table circuit and an output for outputting a timing delay signal for delaying a clock by a timing delay corresponding to the binary output of the programmable table circuit. The band-gap reference can be a temperature independent band-gap reference voltage having a constant-voltage value or a temperature dependent band-gap reference current having a constant-current value. A method is also provided for varying a characteristic of a timing delay signal in accordance with variations of the on-chip temperature of an integrated circuit chip. The method includes the steps of generating a reference parameter; sensing the on-chip temperature of the integrated circuit chip by utilizing at least the reference parameter; providing the sensed on-chip temperature as a binary reading; using the binary reading for providing a respective binary code indicating a timing delay; and varying the characteristic of the timing delay signal, such as the signal's rise time, in accordance with the binary code.

33. 发明授权

US06621324B2 Redundant antifuse segments for improved programming efficiency 有权
标题翻译：冗余反熔丝段，以提高编程效率
公开(公告)号：US06621324B2
公开(公告)日：2003-09-16
申请号：US09683808
申请日：2002-02-19
申请人： John A. Fifield , William R. Tonti
发明人： John A. Fifield , William R. Tonti
IPC分类号： H01H3776
CPC分类号： H01L23/5252 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： An antifuse structure for improved programming efficiency is disclosed wherein the antifuse structure including a first node providing a first voltage, a plurality of antifuse elements, and a plurality of first switches. The plurality of antifuse elements are commonly connected to the first node. The plurality of first switches are sequentially activated during a program mode to individually apply the first voltage to each antifuse element. The antifuse structure may include a second node to which a second voltage is provided. Each of the plurality of first switches may be coupled between the second node and a corresponding one of the plurality of antifuse elements. The antifuse structure may also include a third node to which a fuse latch is connected. A plurality of second switches may be coupled between the third node and a corresponding one of the plurality antifuse elements. The plurality of second switches may be simultaneously activated during a read mode.
摘要翻译：公开了一种用于提高编程效率的反熔丝结构，其中反熔丝结构包括提供第一电压的第一节点，多个反熔丝元件和多个第一开关。多个反熔丝元件通常连接到第一节点。多个第一开关在编程模式期间被依次启动，以分别对每个反熔丝元件施加第一电压。反熔丝结构可以包括提供第二电压的第二节点。多个第一开关中的每一个可以耦合在第二节点和多个反熔丝元件中的对应的一个之间。反熔丝结构还可以包括连接熔丝闩锁的第三节点。多个第二开关可以耦合在第三节点和多个反熔丝元件中的对应的一个之间。多个第二开关可以在读取模式期间同时被激活。

34. 发明授权

US06400202B1 Programmable delay element and synchronous DRAM using the same 失效
标题翻译：可编程延迟元件和同步DRAM
公开(公告)号：US06400202B1
公开(公告)日：2002-06-04
申请号：US09988846
申请日：2001-11-19
申请人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
发明人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
IPC分类号： G06F104
CPC分类号： G11C7/222 , G11C7/04 , G11C7/1072 , H03K5/133 , H03K2005/00065
摘要： A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source PET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.
摘要翻译：可编程延迟元件包括电流源场效应晶体管（FET），开关器件，预充电器件和逆变器器件。电流源FET栅极可编程，预定量的电流。耦合到电流源PET的开关装置接收具有第一和第二电压电平的输入信号。当输入信号处于第二电压电平时，预充电装置对耦合到电流源FET的漏极的节点进行预充电。还耦合到电流源FET的漏极的逆变器装置在输入信号处于第一电压电平时输出延迟信号，延迟信号由可编程预定量的电流定义。逆变器装置产生基本上与参数灵敏度（例如温度变化）无关的逆变器开关点。此外，电流源FET相对于本发明的开关器件的放置允许可编程延迟元件快速达到线性和可预测的操作状态。

35. 发明授权

US06373771B1 Integrated fuse latch and shift register for efficient programming and fuse readout 有权
标题翻译：集成保险丝锁存器和移位寄存器，用于高效编程和保险丝读出
公开(公告)号：US06373771B1
公开(公告)日：2002-04-16
申请号：US09765035
申请日：2001-01-17
申请人： John A. Fifield , Wayne F. Ellis , Nicholas M. van Heel
发明人： John A. Fifield , Wayne F. Ellis , Nicholas M. van Heel
IPC分类号： G11C700
CPC分类号： G11C29/52 , G11C17/16 , G11C17/18 , G11C19/00 , G11C29/006 , G11C29/50
摘要： An integrated circuit device that obviates laser programming of a two-state element (e.g., a wire fuse or antifuse) by programming (i.e., changing) the conductive state of the two-state element according to a binary bit of programing data serially scanned in. Thereafter, the device can verify the actual programming of the two-state element by sensing the conducting condition and then serially scanning out the conductive state value of the two-sate element as a binary logic bit). The device provides the functionality of being able to test any on-chip non-memory circuitry that depends on a memory circuit being fully functional and operational while still at the wafer tester and before having to “blow” (i.e., program) any fuses.
摘要翻译：一种集成电路器件，其通过根据串行扫描的编程数据的二进制位编程（即，改变）两状态元件的导通状态来消除双状态元件（例如，线熔丝或反熔丝）的激光编程此后，器件可以通过感测导通条件来验证双态元件的实际编程，然后串行扫描两元件的导通状态值作为二进制逻辑位）。该器件提供了能够测试任何片上非存储器电路的功能，该片上非存储器电路取决于完全功能和可操作的存储器电路，同时仍然在晶片测试器处，并且在必须“吹”（即编程）任何保险丝之前。

36. 发明授权

US5633605A Dynamic bus with singular central precharge 失效
标题翻译：具有单中心预充电的动态总线
公开(公告)号：US5633605A
公开(公告)日：1997-05-27
申请号：US450764
申请日：1995-05-24
申请人： Jeffrey S. Zimmerman , John A. Fifield , Christopher P. Miller , Robert E. Busch
发明人： Jeffrey S. Zimmerman , John A. Fifield , Christopher P. Miller , Robert E. Busch
IPC分类号： G06F3/00 , G06F13/40 , H03K19/0185 , H03K19/0944 , H03K19/096
CPC分类号： G06F13/4077
摘要： A dynamic bus system with a central precharge device is disclosed that utilizes a controller circuit with a one-shot generator and write synchronizing circuits in combination with logic output modules having pull-up/down devices. The issuance of the output enable (OE) signals is interlocked with the turn-off of the precharge. Thus, data is written to the dynamic bus only when the precharge device is inactive, avoiding bus collisions. The resulting circuitry not only ensures the precharging of the bus before the data write to the bus, but will allow the synchronized OE signals to be issued during the same clock phase as the precharge signal.
摘要翻译：公开了一种具有中央预充电装置的动态总线系统，其利用具有单触发发生器的控制器电路和与具有上拉/下拉器件的逻辑输出模块相结合的写入同步电路。输出使能（OE）信号的发出与预充电的关断互锁。因此，仅当预充电设备处于非活动状态时才将数据写入动态总线，避免总线冲突。所产生的电路不仅可以确保在对总线的数据写入之前总线的预充电，而且允许在与预充电信号相同的时钟相位期间发出同步的OE信号。

37. 发明授权

US5561694A Self-timed driver circuit 失效
标题翻译：自定时驱动电路
公开(公告)号：US5561694A
公开(公告)日：1996-10-01
申请号：US506933
申请日：1995-07-26
申请人： John A. Fifield , Glenn P. Giacalone , Peter J. Jenkins
发明人： John A. Fifield , Glenn P. Giacalone , Peter J. Jenkins
IPC分类号： H03K19/017 , H03K19/0185 , H03K19/0175
CPC分类号： H03K19/01721 , H03K19/018521
摘要： A driver circuit provides for selectively changing the state of an output signal, such as a pre-charged dynamic bus signal. The circuit detects whether or not the data is the opposite state as the pre-charged bus signal, and if so, it drives the bus to the appropriate state. The output from the circuit is self-timed when data can be driven onto the bus as soon as data is valid, i.e., data propagates from the input of the circuit to the bus without depending on a clock or other timing edge.
摘要翻译：驱动器电路提供选择性地改变诸如预充电动态总线信号之类的输出信号的状态。电路检测数据是否与预充电总线信号相反，如果是，则将总线驱动到适当的状态。一旦数据有效就可以将数据驱动到总线上，即数据从电路的输入传播到总线，而不依赖于时钟或其他时序边沿，电路的输出是自定时的。

38. 发明授权

US5502940A Composite building element and methods of making and using the same 失效
标题翻译：复合建筑构件及其使用方法
公开(公告)号：US5502940A
公开(公告)日：1996-04-02
申请号：US108109
申请日：1993-08-17
申请人： John A. Fifield
发明人： John A. Fifield
IPC分类号： B28B3/12 , B28B17/00 , B28B19/00 , E04D1/28 , E04D1/00
CPC分类号： E04D1/28 , B28B17/0018 , B28B19/00 , B28B3/123
摘要： A composite roofing element comprises a first layer of aggregate based material, a second layer of material having a density less than that of the first layer and has a wedge shaped region depending from its underside. The wedge shaped region is preferably integral with the second layer which can be made of an expanded polymer, expanded polystyrene being particularly suitable. Overlapping structure on the side edges and a recess in the thick end of the wedge enable adjacent elements to interlock with each other. By using such lightweight roofing elements the requirement for a substantial load bearing supporting structure is reduced.
摘要翻译：复合屋面元件包括第一层聚集体材料，第二层材料的密度小于第一层的密度，并且具有从其下侧垂下的楔形区域。楔形区域优选与可由膨胀聚合物制成的第二层成一体，发泡聚苯乙烯是特别合适的。侧边缘上的重叠结构和楔形物的厚端部中的凹部使相邻的元件彼此互锁。通过使用这种轻质的屋顶元件，减少了对承重支承结构的重要要求。

39. 发明授权

US5268028A Lightweight concrete roof tiles and similar products 失效
标题翻译：轻型混凝土屋顶瓦和类似产品
公开(公告)号：US5268028A
公开(公告)日：1993-12-07
申请号：US965989
申请日：1992-09-24
申请人： John A. Fifield
发明人： John A. Fifield
IPC分类号： C04B28/04 , E04D1/16 , C04B24/34
CPC分类号： C04B28/04 , E04D1/16 , C04B2111/00594 , Y02W30/92
摘要： A lightweight concrete product in the form of a concrete roof tile is made from a cementitious mixture comprising a porous lightweight aggregate, an hydraulic cement, water, an agent for enhancing, flexural strength and an agent for enhancing the water retention capacity of the lightweight aggregate, the proportions being such that the product has satisfactory impact and flexural strengths.
摘要翻译： PCT No.PCT / GB88 / 00691 Sec。 371日期1989年6月19日 102（e）日期1989年6月19日PCT提交1988年8月22日PCT公布。出版物WO89 / 01918 日期为1989年3月9日。混凝土屋顶瓦形式的轻质混凝土产品由水泥混合物制成，该混凝土包含多孔轻质骨料，水硬性水泥，水，增强抗弯强度的试剂和用于增强轻质骨料的保水能力，使得产品具有令人满意的冲击力和弯曲强度。

40. 发明授权

US5260952A Fault tolerant logic system 失效
标题翻译：容错逻辑系统
公开(公告)号：US5260952A
公开(公告)日：1993-11-09
申请号：US693509
申请日：1991-04-30
申请人： Kenneth E. Beilstein, Jr. , John A. Fifield , Lawrence G. Heller , Hsing-San Lee , Charles H. Stapper
发明人： Kenneth E. Beilstein, Jr. , John A. Fifield , Lawrence G. Heller , Hsing-San Lee , Charles H. Stapper
IPC分类号： G01R31/317 , G06F11/08 , G06F11/10 , G06F11/16 , G11C29/00 , H03K19/00 , H03K19/003 , G01K31/28
CPC分类号： H03K19/00392 , G06F11/1044 , G11C29/84
摘要： A logic system including a first logic block for providing first differential outputs; a second logic block, identical to the first logic block, for providing second differential outputs; a fault detecting device, coupled to the first logic block, for detecting a fault in the first differential outputs; and a selecting device, coupled to the first and second logic blocks and to the fault detecting device, for selecting an output of one of the first and second logic blocks depending on whether the fault detecting device detects a fault.
摘要翻译：一种逻辑系统，包括用于提供第一差分输出的第一逻辑块; 第二逻辑块，与第一逻辑块相同，用于提供第二差分输出; 耦合到第一逻辑块的故障检测装置，用于检测第一差分输出中的故障; 以及耦合到第一和第二逻辑块和故障检测装置的选择装置，用于根据故障检测装置是否检测到故障来选择第一和第二逻辑块之一的输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式