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31. 发明申请

US20140374769A1 GAN-BASED SCHOTTKY BARRIER DIODE WITH ALGAN SURFACE LAYER 有权
标题翻译：基于GAN的肖特基二极管与ALGAN表面层
公开(公告)号：US20140374769A1
公开(公告)日：2014-12-25
申请号：US14479634
申请日：2014-09-08
申请人： Avogy, Inc.
发明人： Richard J. Brown , Thomas R. Prunty , David P. Bour , Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Linda Romano , Madhan Raj
IPC分类号： H01L29/872 , H01L29/47 , H01L29/205 , H01L21/02 , H01L29/66
CPC分类号： H01L29/872 , H01L21/0254 , H01L29/2003 , H01L29/205 , H01L29/475 , H01L29/66143
摘要： A Schottky diode and method of fabricating the Schottky diode using gallium nitride (GaN) materials is disclosed. The method includes providing an n-type GaN substrate having first and second opposing surfaces. The method also includes forming an ohmic metal contact electrically coupled to the first surface, forming an n-type GaN epitaxial layer coupled to the second surface, and forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer. The AlGaN surface layer has a thickness which is less than a critical thickness, and the critical thickness is determined based on an aluminum mole fraction of the AlGaN surface layer. The method also includes forming a Schottky contact electrically coupled to the n-type AlGaN surface layer, where, during operation, an interface between the n-type GaN epitaxial layer and the n-type AlGaN surface layer is substantially free from a two-dimensional electron gas.
摘要翻译：公开了肖特基二极管和使用氮化镓（GaN）材料制造肖特基二极管的方法。该方法包括提供具有第一和第二相对表面的n型GaN衬底。该方法还包括形成电耦合到第一表面的欧姆金属接触，形成耦合到第二表面的n型GaN外延层，以及形成与n型GaN结合的n型氮化镓铝（AlGaN）表面层 GaN外延层。 AlGaN表面层具有小于临界厚度的厚度，并且基于AlGaN表面层的铝摩尔分数来确定临界厚度。该方法还包括形成电耦合到n型AlGaN表面层的肖特基接触，其中在操作期间，n型GaN外延层和n型AlGaN表面层之间的界面基本上不含二维电子气。

32. 发明申请

US20140191242A1 METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL TRANSISTOR 有权
标题翻译：氮化钛垂直晶体管的方法和系统
公开(公告)号：US20140191242A1
公开(公告)日：2014-07-10
申请号：US13735912
申请日：2013-01-07
申请人： AVOGY, INC.
发明人： Hui Nie , Andrew P. Edwards , Isik Kizilyalli , David P. Bour , Thomas R. Prunty , Quentin Diduck
IPC分类号： H01L29/66 , H01L29/808
CPC分类号： H01L29/66462 , H01L21/02389 , H01L21/0254 , H01L29/045 , H01L29/0696 , H01L29/122 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/66431 , H01L29/66909 , H01L29/66924 , H01L29/8083
摘要： A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.
摘要翻译：垂直JFET包括包括JFET的漏极和耦合到GaN衬底的多个图案化外延层的GaN衬底。远端外延层包括源通道的第一部分，并且相邻的图案化外延层被具有预定距离的间隙分开。垂直JFET还包括耦合到远端外延层并且设置在间隙的至少一部分中的多个再生长的外延层。近端再生长的外延层包括源通道的第二部分。垂直JFET还包括通过远端再生长外延层的部分并与源极沟道电接触的源极接触，与远端再生长外延层电接触的栅极接触，以及与GaN衬底电接触的漏极接触。

33. 发明申请

US20140159051A1 MONOLITHICALLY INTEGRATED VERTICAL JFET AND SCHOTTKY DIODE 有权
标题翻译：单相整体垂直JFET和肖特基二极管
公开(公告)号：US20140159051A1
公开(公告)日：2014-06-12
申请号：US13935345
申请日：2013-07-03
申请人： AVOGY, INC.
发明人： Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Linda Romano , David P. Bour , Richard J. Brown , Thomas R. Prunty
IPC分类号： H01L29/808 , H01L27/06 , H01L29/20 , H01L29/66
CPC分类号： H01L29/66909 , H01L21/823487 , H01L27/0605 , H01L27/0611 , H01L27/0629 , H01L27/0727 , H01L27/098 , H01L29/2003 , H01L29/66143 , H01L29/8083 , H01L29/872
摘要： An integrated device including a vertical III-nitride FET and a Schottky diode includes a drain comprising a first III-nitride material, a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, and a channel region comprising a third III-nitride material coupled to the drift region. The integrated device also includes a gate region at least partially surrounding the channel region, a source coupled to the channel region, and a Schottky contact coupled to the drift region. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride FET and the Schottky diode is along the vertical direction.
摘要翻译：包括垂直III族氮化物FET和肖特基二极管的集成器件包括：包括第一III族氮化物材料的漏极，包括耦合到漏极并沿垂直方向邻近漏极设置的第二III族氮化物材料的漂移区，以及包括耦合到所述漂移区的第三III族氮化物材料的沟道区。集成器件还包括至少部分地围绕沟道区的栅极区域，耦合到沟道区的源极和耦合到漂移区域的肖特基接触。沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直III族氮化物FET和肖特基二极管的工作期间的电流沿垂直方向。

34. 发明申请

US20140051236A1 GAN-BASED SCHOTTKY BARRIER DIODE WITH FIELD PLATE 审中-公开
标题翻译：基于GAN的肖特基二极管与现场板
公开(公告)号：US20140051236A1
公开(公告)日：2014-02-20
申请号：US14062724
申请日：2013-10-24
申请人： AVOGY, INC.
发明人： Madhan Raj , Richard J. Brown , Thomas R. Prunty , David P. Bour , Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Linda Romano
IPC分类号： H01L29/66
CPC分类号： H01L29/66143 , H01L29/0661 , H01L29/2003 , H01L29/402 , H01L29/66212 , H01L29/872
摘要： A method for fabricating a III-nitride semiconductor device includes providing a III-nitride substrate having a first surface and a second surface opposing the first surface, forming a III-nitride epitaxial layer coupled to the first surface of the III-nitride substrate, and removing at least a portion of the III-nitride epitaxial layer to form a first exposed surface. The method further includes forming a dielectric layer coupled to the first exposed surface, removing at least a portion of the dielectric layer, and forming a metallic layer coupled to a remaining portion of the dielectric layer such that the remaining portion of the dielectric layer is disposed between the III-nitride epitaxial layer and the metallic layer.
摘要翻译：一种制造III族氮化物半导体器件的方法包括提供具有第一表面和与第一表面相对的第二表面的III族氮化物衬底，形成耦合到III族氮化物衬底的第一表面的III族氮化物外延层，以及去除所述III族氮化物外延层的至少一部分以形成第一暴露表面。该方法还包括形成耦合到第一暴露表面的电介质层，去除电介质层的至少一部分，以及形成耦合到电介质层的剩余部分的金属层，使得电介质层的剩余部分被布置在III族氮化物外延层和金属层之间。

35. 发明授权

US09502544B2 Method and system for planar regrowth in GaN electronic devices 有权
标题翻译： GaN电子器件中平面再生长的方法和系统
公开(公告)号：US09502544B2
公开(公告)日：2016-11-22
申请号：US14815780
申请日：2015-07-31
申请人： AVOGY, INC.
发明人： Isik C. Kizilyalli , Linda Romano , David P. Bour
IPC分类号： H01L29/15 , H01L29/66 , H01L29/78 , H01L29/808 , H01L29/20
CPC分类号： H01L29/66924 , H01L29/2003 , H01L29/66446 , H01L29/7832 , H01L29/8083
摘要： A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources.
摘要翻译：垂直JFET包括III族氮化物衬底和与III族氮化物衬底耦合的第一导电类型的III族氮化物外延层。第一III族氮化物外延层具有第一掺杂剂浓度。垂直JFET还包括耦合到第一III族氮化物外延层的III族氮化物外延结构。 III族氮化物外延结构包括一组第一导电类型的沟道并且具有第二掺杂剂浓度，第一导电类型的一组源，其具有大于第一掺杂剂浓度的第三掺杂剂浓度，并且各自的特征在于：接触表面，以及一组重新生长的门，散布在通道组之间。该组再生栅极的上表面与该组源的接触表面基本共面。

36. 发明授权

US09368582B2 High power gallium nitride electronics using miscut substrates 有权
标题翻译：大功率氮化镓电子器件使用miscut衬底
公开(公告)号：US09368582B2
公开(公告)日：2016-06-14
申请号：US14071032
申请日：2013-11-04
申请人： AVOGY, INC.
发明人： Isik C. Kizilyalli , David P. Bour , Thomas R. Prunty , Gangfeng Ye
IPC分类号： H01L29/20 , H01L29/66 , H01L29/861 , H01L21/02 , H01L21/76 , H01L29/04 , H01L29/06
CPC分类号： H01L29/66204 , H01L21/02389 , H01L21/0243 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/02634 , H01L21/7605 , H01L29/045 , H01L29/0649 , H01L29/0657 , H01L29/2003 , H01L29/6609 , H01L29/861 , H01L29/8613
摘要： An electronic device includes a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the direction of between 0.15° and 0.65°. The electronic device also includes a first epitaxial layer coupled to the III-V substrate and a second epitaxial layer coupled to the first epitaxial layer. The electronic device further includes a first contact in electrical contact with the substrate and a second contact in electrical contact with the second epitaxial layer.
摘要翻译：一种电子器件包括具有六方晶系结构的III-V衬底和与生长表面垂直的III-V衬底，其特征在于从<0001>方向在0.15°至0.65°之间的取向偏差。电子器件还包括耦合到III-V衬底的第一外延层和耦合到第一外延层的第二外延层。电子器件还包括与衬底电接触的第一触点和与第二外延层电接触的第二触点。

37. 发明授权

US09330918B2 Edge termination by ion implantation in gallium nitride 有权
标题翻译：通过离子注入在氮化镓中的边缘终止
公开(公告)号：US09330918B2
公开(公告)日：2016-05-03
申请号：US14558393
申请日：2014-12-02
申请人： Avogy, Inc.
发明人： Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Linda Romano , David P. Bour , Richard J. Brown , Thomas R. Prunty
IPC分类号： H01L21/265 , H01L29/66 , H01L29/808 , H01L29/868 , H01L29/872 , H01L29/06 , H01L29/20
CPC分类号： H01L21/2654 , H01L29/0619 , H01L29/0642 , H01L29/2003 , H01L29/66143 , H01L29/6631 , H01L29/66446 , H01L29/66856 , H01L29/8083 , H01L29/868 , H01L29/872
摘要： A method of making an edge terminated semiconductor device includes providing a GaN substrate having a GaN epitaxial layer grown thereon and exposing a portion of the GaN epitaxial layer to ion implantation. The energy dose is selected to provide a resistivity that is at least 90% of maximum achievable resistivity. The method also includes depositing a conductive layer over a portion of the implanted region.
摘要翻译：制造边缘端接的半导体器件的方法包括提供其上生长有GaN外延层的GaN衬底，并将GaN外延层的一部分暴露于离子注入。选择能量剂量以提供至少达到最大可实现电阻率的90％的电阻率。该方法还包括在植入区域的一部分上沉积导电层。

38. 发明授权

US09287389B2 Method and system for doping control in gallium nitride based devices 有权
标题翻译：在氮化镓基器件中掺杂控制的方法和系统
公开(公告)号：US09287389B2
公开(公告)日：2016-03-15
申请号：US14611041
申请日：2015-01-30
申请人： Avogy, Inc.
发明人： Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Linda Romano , David P. Bour , Richard J. Brown , Thomas R. Prunty
IPC分类号： H01L29/20 , H01L29/772 , H01L21/20 , H01L29/66 , H01L21/02 , H01L29/808 , H01L29/872 , H01L29/10
CPC分类号： H01L29/66909 , H01L21/02538 , H01L21/0254 , H01L21/02573 , H01L21/0262 , H01L29/1066 , H01L29/2003 , H01L29/66212 , H01L29/66893 , H01L29/66924 , H01L29/8083 , H01L29/872
摘要： A method of growing a III-nitride-based epitaxial structure is disclosed. The method includes forming a GaN-based drift layer coupled to the GaN-based substrate, where forming the GaN-based drift layer comprises doping the drift layer with indium to cause the indium concentration of the drift layer to be less than about 1×1016 cm−3 and to cause the carbon concentration of the drift layer to be less than about 1×1016 cm−3. The method also includes forming an n-type channel layer coupled to the GaN-based drift layer, forming an n-contact layer coupled to the GaN-based drift layer, and forming a second electrical contact electrically coupled to the n-contact layer.
摘要翻译：公开了一种生长III族氮化物基外延结构的方法。该方法包括形成耦合到GaN基衬底的GaN基漂移层，其中形成GaN基漂移层包括用铟掺杂漂移层以使漂移层的铟浓度小于约1×1016 cm -3，并使漂移层的碳浓度小于约1×10 16 cm -3。该方法还包括形成耦合到GaN基漂移层的n型沟道层，形成耦合到GaN基漂移层的n型接触层，以及形成电耦合到n型接触层的第二电接触。

39. 发明授权

US09059199B2 Method and system for a gallium nitride vertical transistor 有权
标题翻译：氮化镓垂直晶体管的方法和系统
公开(公告)号：US09059199B2
公开(公告)日：2015-06-16
申请号：US13735912
申请日：2013-01-07
申请人： AVOGY, Inc.
发明人： Hui Nie , Andrew P. Edwards , Isik Kizilyalli , David P. Bour , Thomas R. Prunty , Quentin Diduck
IPC分类号： H01L29/66 , H01L29/808
CPC分类号： H01L29/66462 , H01L21/02389 , H01L21/0254 , H01L29/045 , H01L29/0696 , H01L29/122 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/66431 , H01L29/66909 , H01L29/66924 , H01L29/8083
摘要： A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.
摘要翻译：垂直JFET包括包括JFET的漏极和耦合到GaN衬底的多个图案化外延层的GaN衬底。远端外延层包括源通道的第一部分，并且相邻的图案化外延层被具有预定距离的间隙分开。垂直JFET还包括耦合到远端外延层并且设置在间隙的至少一部分中的多个再生长的外延层。近端再生长的外延层包括源通道的第二部分。垂直JFET还包括通过远端再生长外延层的部分并与源极沟道电接触的源极接触，与远端再生长的外延层电接触的栅极接触，以及与GaN衬底电接触的漏极接触。

40. 发明申请

US20140287570A1 METHOD OF FABRICATING A GALLIUM NITRIDE MERGED P-I-N SCHOTTKY (MPS) DIODE 有权
标题翻译：氮化镓合并P-I-N肖特基（MPS）二极体的制备方法
公开(公告)号：US20140287570A1
公开(公告)日：2014-09-25
申请号：US14299773
申请日：2014-06-09
申请人： Avogy, Inc.
发明人： Andrew P. Edwards , Hui Nie , Isik C. Kizilyalli , Linda Romano , David P. Bour , Richard J. Brown , Thomas R. Prunty
IPC分类号： H01L29/66 , H01L29/872 , H01L29/868 , H01L29/47
CPC分类号： H01L29/66143 , H01L21/046 , H01L21/0495 , H01L29/2003 , H01L29/47 , H01L29/475 , H01L29/868 , H01L29/872
摘要： A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial structure including a first III-nitride epitaxial layer coupled to the first side of the III-nitride substrate and a plurality of III-nitride regions of a second conductivity type. The plurality of III-nitride regions have at least one III-nitride epitaxial region of the first conductivity type between each of the plurality of III-nitride regions. The semiconductor structure further includes a first metallic structure electrically coupled to one or more of the plurality of III-nitride regions and the at least one III-nitride epitaxial region. A Schottky contact is created between the first metallic structure and the at least one III-nitride epitaxial region.
摘要翻译：半导体结构包括具有第一侧和与第一侧相对的第二侧的III族氮化物衬底。 III族氮化物衬底的特征在于第一导电类型和第一掺杂剂浓度。半导体结构还包括III族氮化物外延结构，其包括耦合到III族氮化物衬底的第一侧的第一III族氮化物外延层和多个第二导电类型的III族氮化物区域。多个III族氮化物区域在多个III族氮化物区域中的每一个之间具有至少一个第一导电类型的III族氮化物外延区域。半导体结构还包括电耦合到多个III族氮化物区域和至少一个III族氮化物外延区域中的一个或多个的第一金属结构。在第一金属结构和至少一个III族氮化物外延区之间产生肖特基接触。

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