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1. 发明授权

US08823140B2 GaN vertical bipolar transistor 有权
标题翻译： GaN垂直双极晶体管
公开(公告)号：US08823140B2
公开(公告)日：2014-09-02
申请号：US13675916
申请日：2012-11-13
申请人： Avogy, Inc.
发明人： Hui Nie , Andrew Edwards , Isik Kizilyalli , Dave Bour
IPC分类号： H01L29/66
CPC分类号： H01L21/04 , H01L29/0615 , H01L29/2003 , H01L29/42304 , H01L29/66318 , H01L29/732 , H01L29/7371
摘要： An embodiment of a semiconductor device includes a III-nitride base structure of a first conductivity type, and a III-nitride emitter structure of a second conductivity type having a first surface and a second surface. The second surface is substantially opposite the first surface. The first surface of the III-nitride emitter structure is coupled to a surface of the III-nitride base structure. The semiconductor also includes a first dielectric layer coupled to the second surface of the III-nitride emitter structure, and a spacer coupled to a sidewall of the III-nitride emitter structure and the surface of the III-nitride base structure. The semiconductor also includes a base contact structure with a III-nitride material coupled to the spacer, the surface of the III-nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the III-nitride emitter structure.
摘要翻译：半导体器件的实施例包括第一导电类型的III族氮化物基底结构和具有第一表面和第二表面的第二导电类型的III族氮化物发射极结构。第二表面基本上与第一表面相对。 III族氮化物发射极结构的第一表面耦合到III族氮化物基底结构的表面。半导体还包括耦合到III族氮化物发射极结构的第二表面的第一电介质层和耦合到III族氮化物发射极结构的侧壁和III族氮化物基底结构的表面的间隔物。该半导体还包括具有连接到间隔物，III族氮化物基底结构的表面和第一介电层的III族氮化物材料的基底接触结构，使得第一介电层和间隔物设置在基底触点结构和III族氮化物发射极结构。

2. 发明申请

US20160241148A1 METHOD AND SYSTEM FOR INTEGRATED POWER SUPPLY WITH ACCESSORY FUNCTIONS 审中-公开
标题翻译：具有附件功能的集成电源的方法和系统
公开(公告)号：US20160241148A1
公开(公告)日：2016-08-18
申请号：US15042421
申请日：2016-02-12
申请人： Avogy, Inc.
发明人： Isik Kizilyalli , Dinesh Ramanathan , Rob Levine , Mikhail Guz
IPC分类号： H02M3/335 , H05K5/02 , H02M7/00
CPC分类号： H05K5/0247 , H02M3/33523 , H02M2001/0025 , H02M2001/007
摘要： A variable output power supply includes a power unit comprising a housing including an output port, one or more accessories disposed in the housing, and a controller disposed in the housing and in communication with the output port. The variable output power supply also includes a power cable. The controller is operable to modify operation of the output port in response, at least in part, to insertion of the power cable in the output port.
摘要翻译：可变输出电源包括动力单元，其包括壳体，该壳体包括输出端口，设置在壳体中的一个或多个附件，以及布置在壳体中并与输出端口连通的控制器。可变输出电源还包括电源线。控制器可操作以至少部分地修改输出端口的操作以将电力电缆插入输出端口。

3. 发明申请

US20140191242A1 METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL TRANSISTOR 有权
标题翻译：氮化钛垂直晶体管的方法和系统
公开(公告)号：US20140191242A1
公开(公告)日：2014-07-10
申请号：US13735912
申请日：2013-01-07
申请人： AVOGY, INC.
发明人： Hui Nie , Andrew P. Edwards , Isik Kizilyalli , David P. Bour , Thomas R. Prunty , Quentin Diduck
IPC分类号： H01L29/66 , H01L29/808
CPC分类号： H01L29/66462 , H01L21/02389 , H01L21/0254 , H01L29/045 , H01L29/0696 , H01L29/122 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/66431 , H01L29/66909 , H01L29/66924 , H01L29/8083
摘要： A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.
摘要翻译：垂直JFET包括包括JFET的漏极和耦合到GaN衬底的多个图案化外延层的GaN衬底。远端外延层包括源通道的第一部分，并且相邻的图案化外延层被具有预定距离的间隙分开。垂直JFET还包括耦合到远端外延层并且设置在间隙的至少一部分中的多个再生长的外延层。近端再生长的外延层包括源通道的第二部分。垂直JFET还包括通过远端再生长外延层的部分并与源极沟道电接触的源极接触，与远端再生长外延层电接触的栅极接触，以及与GaN衬底电接触的漏极接触。

4. 发明授权

US09472684B2 Lateral GaN JFET with vertical drift region 有权
标题翻译：具有垂直漂移区域的横向GaN JFET
公开(公告)号：US09472684B2
公开(公告)日：2016-10-18
申请号：US13675826
申请日：2012-11-13
申请人： AVOGY, INC.
发明人： Hui Nie , Andrew Edwards , Isik Kizilyalli , Dave Bour , Thomas R. Prunty
IPC分类号： H01L29/808 , H01L29/66 , H01L29/10 , H01L29/20
CPC分类号： H01L29/8083 , H01L29/1066 , H01L29/2003 , H01L29/66909
摘要： A gallium nitride (GaN)-based junction field-effect transistor (JFET) can include a GaN drain region having a top surface extending in a lateral dimension, a source region, and a GaN channel region of a first conductivity type coupled between the source region and the GaN drain region and operable to conduct electrical current between the source region and the GaN drain region. The JFET can also include a blocking layer disposed between the source region and the GaN drain region such that the GaN channel region is operable to conduct the electrical current substantially along the lateral dimension in a laterally-conductive region of the GaN channel region, and a GaN gate region of a second conductivity type coupled to the GaN channel region such that the laterally-conductive region of the GaN channel region is disposed between at least a portion of the blocking layer and the GaN gate region.
摘要翻译：基于氮化镓（GaN）的结场效应晶体管（JFET）可以包括具有在横向尺寸上延伸的顶表面的GaN漏极区域，源极区域和耦合在源极之间的第一导电类型的GaN沟道区域区域和GaN漏极区域并且可操作以在源极区域和GaN漏极区域之间传导电流。 JFET还可以包括设置在源极区域和GaN漏极区域之间的阻挡层，使得GaN沟道区域可操作地在GaN沟道区域的横向导电区域中沿着横向尺寸传导电流，并且 GaN栅极区域，其耦合到GaN沟道区域，使得GaN沟道区域的横向导电区域设置在阻挡层的至少一部分和GaN栅极区域之间。

5. 发明申请

US20140191241A1 GALLIUM NITRIDE VERTICAL JFET WITH HEXAGONAL CELL STRUCTURE 审中-公开
标题翻译：具有六角形细胞结构的硝酸锌垂直JFET
公开(公告)号：US20140191241A1
公开(公告)日：2014-07-10
申请号：US13735897
申请日：2013-01-07
申请人： AVOGY, INC.
发明人： Andrew P. Edwards , Hui Nie , Donald R. Disney , Isik Kizilyalli
IPC分类号： H01L27/098
CPC分类号： H01L27/098 , H01L29/0692 , H01L29/2003 , H01L29/42312 , H01L29/66909 , H01L29/8083
摘要： An array of GaN-based vertical JFETs includes a GaN substrate comprising a drain of one or more of the JFETs and one or more epitaxial layers coupled to the GaN substrate. The array also includes a plurality of hexagonal cells coupled to the one or more epitaxial layers and extending in a direction normal to the GaN substrate. Sidewalls of the plurality of hexagonal cells are substantially aligned with respect to crystal planes of the GaN substrate. The array further includes a plurality of channel regions, each having a portion adjacent a sidewall of the plurality of hexagonal cells, a plurality of gate regions of one or more of the JFETs, each electrically coupled to one or more of the plurality of channel regions, and a plurality of source regions of one or more of the JFETs electrically coupled to one or more of the plurality of channel regions.
摘要翻译： GaN基垂直JFET的阵列包括包含一个或多个JFET的漏极和耦合到GaN衬底的一个或多个外延层的GaN衬底。该阵列还包括耦合到一个或多个外延层并沿垂直于GaN衬底的方向延伸的多个六边形单元。多个六边形单元的侧壁相对于GaN衬底的晶面基本上对齐。阵列还包括多个通道区域，每个沟道区域具有邻近多个六边形单元的侧壁的部分，一个或多个JFET的多个栅极区域，每个栅极区域电耦合到多个沟道区域中的一个或多个以及电耦合到多个沟道区中的一个或多个的一个或多个JFET的多个源极区。

6. 发明申请

US20140131837A1 GAN VERTICAL BIPOLAR TRANSISTOR 有权
标题翻译： GAN垂直双极晶体管
公开(公告)号：US20140131837A1
公开(公告)日：2014-05-15
申请号：US13675916
申请日：2012-11-13
申请人： AVOGY, INC.
发明人： Hui Nie , Andrew Edwards , Isik Kizilyalli , Dave Bour
IPC分类号： H01L29/73 , H01L21/04
CPC分类号： H01L21/04 , H01L29/0615 , H01L29/2003 , H01L29/42304 , H01L29/66318 , H01L29/732 , H01L29/7371
摘要： An embodiment of a semiconductor device includes a III-nitride base structure of a first conductivity type, and a III-nitride emitter structure of a second conductivity type having a first surface and a second surface. The second surface is substantially opposite the first surface. The first surface of the III-nitride emitter structure is coupled to a surface of the III-nitride base structure. The semiconductor also includes a first dielectric layer coupled to the second surface of the III-nitride emitter structure, and a spacer coupled to a sidewall of the III-nitride emitter structure and the surface of the III-nitride base structure. The semiconductor also includes a base contact structure with a III-nitride material coupled to the spacer, the surface of the III-nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the III-nitride emitter structure.
摘要翻译：半导体器件的实施例包括第一导电类型的III族氮化物基底结构和具有第一表面和第二表面的第二导电类型的III族氮化物发射极结构。第二表面基本上与第一表面相对。 III族氮化物发射极结构的第一表面耦合到III族氮化物基底结构的表面。半导体还包括耦合到III族氮化物发射极结构的第二表面的第一电介质层和耦合到III族氮化物发射极结构的侧壁和III族氮化物基底结构的表面的间隔物。该半导体还包括具有连接到间隔物，III族氮化物基底结构的表面和第一介电层的III族氮化物材料的基底接触结构，使得第一介电层和间隔物设置在基底触点结构和III族氮化物发射极结构。

7. 发明授权

US09059199B2 Method and system for a gallium nitride vertical transistor 有权
标题翻译：氮化镓垂直晶体管的方法和系统
公开(公告)号：US09059199B2
公开(公告)日：2015-06-16
申请号：US13735912
申请日：2013-01-07
申请人： AVOGY, Inc.
发明人： Hui Nie , Andrew P. Edwards , Isik Kizilyalli , David P. Bour , Thomas R. Prunty , Quentin Diduck
IPC分类号： H01L29/66 , H01L29/808
CPC分类号： H01L29/66462 , H01L21/02389 , H01L21/0254 , H01L29/045 , H01L29/0696 , H01L29/122 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/66431 , H01L29/66909 , H01L29/66924 , H01L29/8083
摘要： A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.
摘要翻译：垂直JFET包括包括JFET的漏极和耦合到GaN衬底的多个图案化外延层的GaN衬底。远端外延层包括源通道的第一部分，并且相邻的图案化外延层被具有预定距离的间隙分开。垂直JFET还包括耦合到远端外延层并且设置在间隙的至少一部分中的多个再生长的外延层。近端再生长的外延层包括源通道的第二部分。垂直JFET还包括通过远端再生长外延层的部分并与源极沟道电接触的源极接触，与远端再生长的外延层电接触的栅极接触，以及与GaN衬底电接触的漏极接触。

8. 发明申请

US20150243758A1 METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL TRANSISTOR 审中-公开
标题翻译：氮化钛垂直晶体管的方法和系统
公开(公告)号：US20150243758A1
公开(公告)日：2015-08-27
申请号：US14711547
申请日：2015-05-13
申请人： AVOGY, Inc.
发明人： Hui Nie , Andrew P. Edwards , Isik Kizilyalli , David P. Bour , Thomas R. Prunty , Quentin Diduck
IPC分类号： H01L29/66 , H01L29/201 , H01L29/06 , H01L29/808 , H01L21/02 , H01L29/20 , H01L29/205
CPC分类号： H01L29/66462 , H01L21/02389 , H01L21/0254 , H01L29/045 , H01L29/0696 , H01L29/122 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/66431 , H01L29/66909 , H01L29/66924 , H01L29/8083
摘要： A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.
摘要翻译：垂直JFET包括包括JFET的漏极和耦合到GaN衬底的多个图案化外延层的GaN衬底。远端外延层包括源通道的第一部分，并且相邻的图案化外延层被具有预定距离的间隙分开。垂直JFET还包括耦合到远端外延层并且设置在间隙的至少一部分中的多个再生长的外延层。近端再生长的外延层包括源通道的第二部分。垂直JFET还包括通过远端再生长外延层的部分并与源极沟道电接触的源极接触，与远端再生长的外延层电接触的栅极接触，以及与GaN衬底电接触的漏极接触。

9. 发明申请

US20140131721A1 LATERAL GAN JFET WITH VERTICAL DRIFT REGION 有权
标题翻译：具有垂直移动区域的横向连杆
公开(公告)号：US20140131721A1
公开(公告)日：2014-05-15
申请号：US13675826
申请日：2012-11-13
申请人： AVOGY, INC.
发明人： Hui Nie , Andrew Edwards , Isik Kizilyalli , Dave Bour , Thomas R. Prunty
IPC分类号： H01L29/808 , H01L29/20
CPC分类号： H01L29/8083 , H01L29/1066 , H01L29/2003 , H01L29/66909
摘要： A gallium nitride (GaN)-based junction field-effect transistor (JFET) can include a GaN drain region having a top surface extending in a lateral dimension, a source region, and a GaN channel region of a first conductivity type coupled between the source region and the GaN drain region and operable to conduct electrical current between the source region and the GaN drain region. The JFET can also include a blocking layer disposed between the source region and the GaN drain region such that the GaN channel region is operable to conduct the electrical current substantially along the lateral dimension in a laterally-conductive region of the GaN channel region, and a GaN gate region of a second conductivity type coupled to the GaN channel region such that the laterally-conductive region of the GaN channel region is disposed between at least a portion of the blocking layer and the GaN gate region.
摘要翻译：基于氮化镓（GaN）的结场效应晶体管（JFET）可以包括具有在横向尺寸上延伸的顶表面的GaN漏极区域，源极区域和耦合在源极之间的第一导电类型的GaN沟道区域区域和GaN漏极区域并且可操作以在源极区域和GaN漏极区域之间传导电流。 JFET还可以包括设置在源极区域和GaN漏极区域之间的阻挡层，使得GaN沟道区域可操作地在GaN沟道区域的横向导电区域中沿着横向尺寸传导电流，并且 GaN栅极区域，其耦合到GaN沟道区域，使得GaN沟道区域的横向导电区域设置在阻挡层的至少一部分和GaN栅极区域之间。

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