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    • 34. 发明授权
    • Transistor, a transistor arrangement and method thereof
    • 晶体管,晶体管结构及其方法
    • US08143677B2
    • 2012-03-27
    • US12659107
    • 2010-02-25
    • Myoung-Soo Kim
    • Myoung-Soo Kim
    • H01L29/76H01L29/94H01L31/062H01L31/113H01L31/119
    • H01L29/7833H01L29/41758H01L29/66575
    • A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted. The example transistor may include a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer.
    • 提供一种晶体管,晶体管结构及其方法。 示例性方法可以包括确定晶体管的栅极宽度是否已被调整; 以及如果所述确定步骤确定所述晶体管的栅极宽度,则基于所述调整的栅极宽度来调整所述晶体管的高浓度杂质掺杂区域和所述晶体管的器件隔离层之间的距离。 示例性晶体管可以包括限定第一有源区的第一器件隔离层,具有第一栅极宽度并与第一有源区交叉的第一栅极线,首先在第一有源区中形成的第一低浓度杂质掺杂区 和第一栅极线的第二面和形成在低浓度杂质掺杂区域中的第一较高浓度杂质掺杂区,并且不与栅极线和器件隔离层接触。
    • 35. 发明申请
    • METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET) AND METHOD OF FABRICATING THE SAME
    • 金属氧化物半导体场效应晶体管(MOSFET)及其制造方法
    • US20090263948A1
    • 2009-10-22
    • US12498000
    • 2009-07-06
    • Myoung-Soo KIM
    • Myoung-Soo KIM
    • H01L21/8234H01L21/336
    • H01L21/823462H01L21/823456
    • A Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) is provided. The MOSFET includes a semiconductor substrate, a device isolating region disposed on a predetermined portion of the semiconductor substrate to define an active region, a source region and a drain region spaced apart from each other about a channel region within the active region, and a gate electrode formed on the active region between the source region and the drain region. Furthermore, the MOSFET also includes a gate insulating layer formed between the active region and the gate electrode. The gate insulating layer includes a central gate insulating layer disposed under central portion of the gate electrode, an edge gate insulating layer disposed under an edge portion of the gate electrode to have a bottom surface level with a bottom of the central gate insulating layer and an upper surface protruding to be higher than an upper surface of the central gate insulating layer.
    • 提供金属氧化物半导体场效应晶体管(MOSFET)。 MOSFET包括半导体衬底,设置在半导体衬底的预定部分上以限定有源区的器件隔离区,围绕有源区内的沟道区彼此隔开的源区和漏区,以及栅极 在源极区域和漏极区域之间的有源区域上形成电极。 此外,MOSFET还包括在有源区和栅电极之间形成的栅极绝缘层。 所述栅极绝缘层包括设置在所述栅极电极的中心部分的中心栅极绝缘层,设置在所述栅极电极的边缘部分下方的边缘栅极绝缘层,以具有与所述中心栅极绝缘层的底部相对的底面电平, 上表面突出高于中心栅极绝缘层的上表面。
    • 37. 发明申请
    • Metal oxide semiconductor field-effect transistor (MOSFET) and method of fabricating the same
    • 金属氧化物半导体场效应晶体管(MOSFET)及其制造方法
    • US20060278920A1
    • 2006-12-14
    • US11443385
    • 2006-05-30
    • Myoung-Soo Kim
    • Myoung-Soo Kim
    • H01L21/8234
    • H01L21/823462H01L21/823456
    • A Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) is provided. The MOSFET includes a semiconductor substrate, a device isolating region disposed on a predetermined portion of the semiconductor substrate to define an active region, a source region and a drain region spaced apart from each other about a channel region within the active region, and a gate electrode formed on the active region between the source region and the drain region. Furthermore, the MOSFET also includes a gate insulating layer formed between the active region and the gate electrode. The gate insulating layer includes a central gate insulating layer disposed under central portion of the gate electrode, an edge gate insulating layer disposed under an edge portion of the gate electrode to have a bottom surface level with a bottom of the central gate insulating layer and an upper surface protruding to be higher than an upper surface of the central gate insulating layer.
    • 提供金属氧化物半导体场效应晶体管(MOSFET)。 MOSFET包括半导体衬底,设置在半导体衬底的预定部分上以限定有源区域的器件隔离区域,围绕有源区域内的沟道区域彼此间隔开的源极区域和漏极区域,以及栅极 在源极区域和漏极区域之间的有源区域上形成电极。 此外,MOSFET还包括在有源区和栅电极之间形成的栅极绝缘层。 所述栅极绝缘层包括设置在所述栅极电极的中心部分的中心栅极绝缘层,设置在所述栅极电极的边缘部分下方的边缘栅极绝缘层,以具有与所述中心栅极绝缘层的底部的底面水平面, 上表面突出高于中心栅极绝缘层的上表面。
    • 38. 发明申请
    • Catalyst enhanced chemical vapor deposition apparatus and deposition method using the same
    • 催化剂增强化学气相沉积装置及其沉积方法
    • US20060254513A1
    • 2006-11-16
    • US11405552
    • 2006-04-18
    • Hee-Cheol KangKazuo FurunoHan-Ki KimMyoung-Soo Kim
    • Hee-Cheol KangKazuo FurunoHan-Ki KimMyoung-Soo Kim
    • C23C16/00
    • C23C16/44C23C16/46
    • A catalyst-enhanced chemical vapor deposition (CECVD) apparatus and a deposition method, in which tension is applied to a catalyst wire in order to prevent the catalyst wire from sagging due to thermal deformation, and additional gas is used to prevent foreign material from being generated. The CECVD apparatus may be constructed with a process chamber, a showerhead to introduce process gas into process chamber, a tensile catalyst wire structure provided in the process chamber to decompose the gas introduced from the showerhead, and a substrate on which the gas decomposed by the catalyst wire structure is deposited, so that the tension is applied to a catalyst wire in order to prevent the catalyst wire from sagging due to thermal deformation, and additional gas is used to prevent foreign material from being generated, thereby eliminating occurrences of non-uniform temperatures of a substrate and non-uniform film growth, and concomitantly enhancing the durability of the catalyst wire.
    • 催化剂增强化学气相沉积(CECVD)装置和沉积方法,其中向催化剂丝施加张力以防止催化剂丝由于热变形而下垂,并且使用另外的气体来防止异物 生成。 CECVD装置可以构造有处理室,将工艺气体引入处理室的喷头,设置在处理室中的分解从喷头引入的气体的拉伸催化剂丝线结构以及由其分解的气体 催化剂丝线结构被沉积,使得张力被施加到催化剂丝上,以防止催化剂丝由于热变形而下垂,并且使用额外的气体来防止产生异物,从而消除不均匀的发生 底物的温度和不均匀的膜生长,并且伴随地提高催化剂丝的耐久性。
    • 40. 发明申请
    • Semiconductor device including a transistor having low threshold voltage and high breakdown voltage
    • 半导体器件包括具有低阈值电压和高击穿电压的晶体管
    • US20050194648A1
    • 2005-09-08
    • US11066492
    • 2005-02-28
    • Myoung-soo Kim
    • Myoung-soo Kim
    • H01L21/283H01L21/336H01L21/8234H01L27/088H01L29/78
    • H01L21/823418H01L21/823462H01L27/088
    • A semiconductor device, including a transistor having low threshold voltage and high breakdown voltage, includes a first gate electrode, a second gate electrode, and a third gate electrode arranged on a predetermined first, second, and third region of a semiconductor substrate, respectively, a first gate insulating layer, a second gate insulating layer, and a third gate insulating layer, which are interposed between the first, second and third gate electrode and the semiconductor substrate, respectively, and first, second, and third junction regions arranged in the first, second, and third region of the semiconductor substrate, respectively, on both sides of the first, second and third gate electrode, respectively, wherein a thickness of the first gate insulating layer is greater than a thickness of either of the second or third gate insulating layers, and wherein a structure of the first junction region and a structure of the third junction region are the same.
    • 包括具有低阈值电压和高击穿电压的晶体管的半导体器件分别包括布置在半导体衬底的预定第一,第二和第三区域上的第一栅电极,第二栅电极和第三栅电极, 第一栅极绝缘层,第二栅极绝缘层和第三栅极绝缘层,分别介于第一,第二和第三栅电极与半导体衬底之间,第一,第二和第三结区域布置在 分别在第一,第二和第三栅极的两侧分别具有半导体衬底的第一,第二和第三区域,其中第一栅极绝缘层的厚度大于第二栅极绝缘层的厚度 栅极绝缘层,并且其中第一结区域的结构和第三结区域的结构相同。