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1. 发明申请

US20080164469A1 Semiconductor device with measurement pattern in scribe region 审中-公开
标题翻译：具有划线区域测量图案的半导体器件
公开(公告)号：US20080164469A1
公开(公告)日：2008-07-10
申请号：US12005180
申请日：2007-12-26
申请人： Myoung-soo Kim , Yong-chan Kim
发明人： Myoung-soo Kim , Yong-chan Kim
IPC分类号： H01L23/58
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/7084 , H01L22/34 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes pads disposed in a chip region of a semiconductor substrate and line patterns disposed in a scribe region of the semiconductor substrate and extending toward the pads. The line patterns each have a line-width that is less than a predetermined distance between adjacent pads. Thus, respective interconnection lines connected to the pads are not short-circuited to each-other through the line patterns in the remaining scribe region after the chip region is sawed into a semiconductor chip.
摘要翻译：半导体器件包括设置在半导体衬底的芯片区域中的焊盘和设置在半导体衬底的划线区域中且朝向焊盘延伸的线图案。线图案各自具有小于相邻垫之间的预定距离的线宽。因此，在芯片区域被锯成半导体芯片之后，连接到焊盘的各个互连线在剩余划线区域中的线图案之间不会彼此短路。

2. 发明申请

US20050194648A1 Semiconductor device including a transistor having low threshold voltage and high breakdown voltage 有权
标题翻译：半导体器件包括具有低阈值电压和高击穿电压的晶体管
公开(公告)号：US20050194648A1
公开(公告)日：2005-09-08
申请号：US11066492
申请日：2005-02-28
申请人： Myoung-soo Kim
发明人： Myoung-soo Kim
IPC分类号： H01L21/283 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/78
CPC分类号： H01L21/823418 , H01L21/823462 , H01L27/088
摘要： A semiconductor device, including a transistor having low threshold voltage and high breakdown voltage, includes a first gate electrode, a second gate electrode, and a third gate electrode arranged on a predetermined first, second, and third region of a semiconductor substrate, respectively, a first gate insulating layer, a second gate insulating layer, and a third gate insulating layer, which are interposed between the first, second and third gate electrode and the semiconductor substrate, respectively, and first, second, and third junction regions arranged in the first, second, and third region of the semiconductor substrate, respectively, on both sides of the first, second and third gate electrode, respectively, wherein a thickness of the first gate insulating layer is greater than a thickness of either of the second or third gate insulating layers, and wherein a structure of the first junction region and a structure of the third junction region are the same.
摘要翻译：包括具有低阈值电压和高击穿电压的晶体管的半导体器件分别包括布置在半导体衬底的预定第一，第二和第三区域上的第一栅电极，第二栅电极和第三栅电极，第一栅极绝缘层，第二栅极绝缘层和第三栅极绝缘层，分别介于第一，第二和第三栅电极与半导体衬底之间，第一，第二和第三结区域布置在分别在第一，第二和第三栅极的两侧分别具有半导体衬底的第一，第二和第三区域，其中第一栅极绝缘层的厚度大于第二栅极绝缘层的厚度栅极绝缘层，并且其中第一结区域的结构和第三结区域的结构相同。

3. 发明授权

US07217985B2 Semiconductor device including a transistor having low threshold voltage and high breakdown voltage 有权
标题翻译：半导体器件包括具有低阈值电压和高击穿电压的晶体管
公开(公告)号：US07217985B2
公开(公告)日：2007-05-15
申请号：US11066492
申请日：2005-02-28
申请人： Myoung-soo Kim
发明人： Myoung-soo Kim
IPC分类号： H01L29/00
CPC分类号： H01L21/823418 , H01L21/823462 , H01L27/088
摘要： A semiconductor device, including a transistor having low threshold voltage and high breakdown voltage, includes a first gate electrode, a second gate electrode, and a third gate electrode arranged on a predetermined first, second, and third region of a semiconductor substrate, respectively, a first gate insulating layer, a second gate insulating layer, and a third gate insulating layer, which are interposed between the first, second and third gate electrode and the semiconductor substrate, respectively, and first, second, and third junction regions arranged in the first, second, and third region of the semiconductor substrate, respectively, on both sides of the first, second and third gate electrode, respectively, wherein a thickness of the first gate insulating layer is greater than a thickness of either of the second or third gate insulating layers, and wherein a structure of the first junction region and a structure of the third junction region are the same.
摘要翻译：包括具有低阈值电压和高击穿电压的晶体管的半导体器件分别包括布置在半导体衬底的预定第一，第二和第三区域上的第一栅电极，第二栅电极和第三栅电极，第一栅极绝缘层，第二栅极绝缘层和第三栅极绝缘层，分别介于第一，第二和第三栅电极与半导体衬底之间，第一，第二和第三结区域布置在分别在第一，第二和第三栅极的两侧分别具有半导体衬底的第一，第二和第三区域，其中第一栅极绝缘层的厚度大于第二栅极绝缘层的厚度栅极绝缘层，并且其中第一结区域的结构和第三结区域的结构相同。

4. 发明授权

US06962840B2 Method of forming MOS transistor 失效
标题翻译：形成MOS晶体管的方法
公开(公告)号：US06962840B2
公开(公告)日：2005-11-08
申请号：US10659954
申请日：2003-09-11
申请人： Myoung-soo Kim
发明人： Myoung-soo Kim
IPC分类号： H01L21/8234 , H01L27/06 , H01L21/336
CPC分类号： H01L27/0629 , H01L21/823462
摘要： Methods of simultaneously forming MOS transistors and a capacitor on a substrate having gate insulation layers of varying thicknesses are disclosed. A method includes forming field regions in a substrate to define a first transistor region, a capacitor region, and a second transistor region, forming a first gate stack in the first transistor region and a lower electrode in the capacitor region, and forming an upper electrode on the lower electrode with a dielectric layer interposed therebetween and a second gate stack in the second transistor region.
摘要翻译：公开了在具有不同厚度的栅极绝缘层的基板上同时形成MOS晶体管和电容器的方法。一种方法包括在衬底中形成场区以限定第一晶体管区域，电容器区域和第二晶体管区域，在第一晶体管区域中形成第一栅极堆叠以及在电容器区域中形成下电极，以及形成上电极在其上插有电介质层的下电极和在第二晶体管区域中的第二栅极叠层。

5. 发明授权

US06869835B2 Method of forming MOS transistor 有权
标题翻译：形成MOS晶体管的方法
公开(公告)号：US06869835B2
公开(公告)日：2005-03-22
申请号：US10455600
申请日：2003-06-05
申请人： Myoung-soo Kim
发明人： Myoung-soo Kim
IPC分类号： H01L21/02 , H01L21/8234 , H01L27/06 , H01L21/336
CPC分类号： H01L21/823462 , H01L27/0629 , H01L28/40
摘要： Methods of simultaneously forming MOS transistors and a capacitor on a substrate having gate insulation layers of varying thicknesses. A method includes forming field regions in a substrate to define a first transistor region, a capacitor region, and a second transistor region, forming a first gate stack in the first transistor region and a lower electrode in the capacitor region, and forming an upper electrode on the lower electrode with a dielectric layer interposed therebetween and a second gate stack in the second transistor region.
摘要翻译：在具有不同厚度的栅极绝缘层的基板上同时形成MOS晶体管和电容器的方法。一种方法包括在衬底中形成场区以限定第一晶体管区域，电容器区域和第二晶体管区域，在第一晶体管区域中形成第一栅极堆叠以及在电容器区域中形成下电极，以及形成上电极在其上插有电介质层的下电极和在第二晶体管区域中的第二栅极叠层。

6. 发明授权

US06720667B2 Semiconductor device having align key for defining active region and method for manufacturing the same 有权
标题翻译：具有用于定义有源区域的对准键的半导体器件及其制造方法
公开(公告)号：US06720667B2
公开(公告)日：2004-04-13
申请号：US10307806
申请日：2002-12-02
申请人： Myoung-soo Kim
发明人： Myoung-soo Kim
IPC分类号： H01L23544
CPC分类号： H01L23/544 , H01L21/823493 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having an align key, which is simultaneously formed by implanting ions before defining an active region, for a precise alignment with a preformed well on a semiconductor substrate when forming a photoresist pattern for defining the active region, and a method for manufacturing the same are provided The semiconductor device includes the align key formed of a first recess having a first depth from a surface of a semiconductor substrate in a scribe line region of the semiconductor substrate, and a second step portion formed by a second recess having a second depth, which is less than or equal to the first depth, from the surface of the semiconductor substrate in a well region of the semiconductor substrate.
摘要翻译：一种具有对准键的半导体器件，其在形成用于限定有源区域的光致抗蚀剂图案之前通过在限定有源区域之前注入离子而与半导体衬底上的预制阱精确对准而同时形成，以及制造方法半导体器件包括由半导体衬底的划线区域中的半导体衬底的表面具有第一深度的第一凹部形成的对准键和由具有第二深度的第二凹部形成的第二阶梯部分，其在半导体衬底的阱区中从半导体衬底的表面小于或等于第一深度。

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