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31. 发明申请

US20110131459A1 Memory Device with Protection Capability and Method of Accessing Data Therein 有权
标题翻译：具有保护能力的存储设备和访问数据的方法
公开(公告)号：US20110131459A1
公开(公告)日：2011-06-02
申请号：US12626800
申请日：2009-11-27
申请人： Chih-Cheng Tu , Yan-Wun Huang , Han-Lung Huang , Ming-Hung Chou , Chien-Fu Huang , Chih-Hwa Chang
发明人： Chih-Cheng Tu , Yan-Wun Huang , Han-Lung Huang , Ming-Hung Chou , Chien-Fu Huang , Chih-Hwa Chang
IPC分类号： G06F12/14 , H03M13/03 , G06F11/07 , H04L9/20
CPC分类号： G06F11/1068 , G06F21/78 , G06F21/79 , G06F2221/2141 , H03M13/03 , H04L9/0637 , H04L9/0662 , H04L2209/34
摘要： The present invention is directed to a memory device with protection capability and a method of accessing data therein. A spreader encrypts input user data according to an entered password, and the encrypted data is then stored in a storage area. A despreader performs reverse process of the spreader on the stored data according to the entered password.
摘要翻译：本发明涉及一种具有保护能力的存储设备及其中访问数据的方法。扩展器根据输入的密码加密输入用户数据，然后将加密的数据存储在存储区域中。解扩器根据输入的密码对扩展器对存储的数据进行反向处理。

32. 发明授权

US07907445B2 Method and system for obtaining a reference block for a MLC flash memory 有权
标题翻译：用于获得MLC闪存的参考块的方法和系统
公开(公告)号：US07907445B2
公开(公告)日：2011-03-15
申请号：US12486691
申请日：2009-06-17
申请人： Chien-Fu Huang , Ming-Hung Chou , Han-Lung Huang , Shih-Keng Cho
发明人： Chien-Fu Huang , Ming-Hung Chou , Han-Lung Huang , Shih-Keng Cho
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/349 , G11C16/3495
摘要： A method and system for obtaining a reference block on which reference voltages may be found for a MLC flash memory are disclosed. A first block and a second block are provided in the flash memory. A memory controller alternatively controls one of the first and the second blocks to act as the reference block and the other one as a cycle block in a respective period, during which the reference block stays idle and the cycle block is subjected to program/erase cycles.
摘要翻译：公开了一种用于获得参考块的方法和系统，其中可以针对MLC闪速存储器找到参考电压。闪存中提供第一块和第二块。存储器控制器交替地控制第一和第二块中的一个作为参考块，而另一个作为周期块在相应的周期内，在此期间参考块保持空闲并且循环块经受编程/擦除周期。

33. 发明申请

US20110055659A1 Method and System of Dynamic Data Storage for Error Correction in a Memory Device 有权
标题翻译：用于存储器件中纠错的动态数据存储的方法和系统
公开(公告)号：US20110055659A1
公开(公告)日：2011-03-03
申请号：US12548348
申请日：2009-08-26
申请人： Chih-Cheng Tu , Yan-Wun Huang , Han-Lung Huang , Ming-Hung Chou , Chien-Fu Huang , Chih-Hwa Chang
发明人： Chih-Cheng Tu , Yan-Wun Huang , Han-Lung Huang , Ming-Hung Chou , Chien-Fu Huang , Chih-Hwa Chang
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/05 , G06F11/1068 , G11C2029/0411 , H03M13/13
摘要： A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, and the received data is then encoded and associated error correction code (ECC) is generated. The encoded data is stored in a portion of a data partition of the memory device, wherein percentage of the stored data in the data partition is determined according to an amount of corrected errors associated with the data partition or is predetermined.
摘要翻译：公开了一种用于存储器件中的纠错的动态数据存储的方法。接收用于存储的数据，然后对接收到的数据进行编码，并生成相关联的纠错码（ECC）。编码数据被存储在存储器件的数据分区的一部分中，其中数据分区中存储的数据的百分比是根据与数据分区相关联的校正误差的量来确定的或者是预定的。

34. 发明申请

US20060145263A1 Plasma damage protection circuit for protecting multiple word lines or strapped word lines of a memory device 审中-公开
标题翻译：用于保护存储器件的多个字线或带状字线的等离子体损伤保护电路
公开(公告)号：US20060145263A1
公开(公告)日：2006-07-06
申请号：US11029366
申请日：2005-01-06
申请人： Ming-Hung Chou
发明人： Ming-Hung Chou
IPC分类号： H01L23/62
CPC分类号： G11C8/00 , H01L27/0255
摘要： A memory device is connectable to a protection circuit for plasma-induced charge damage protection and includes a memory array including a plurality of word lines and a plurality of diodes each coupled between a corresponding one of the word lines and the protection circuit.
摘要翻译：存储器件可连接到用于等离子体感应的电荷损坏保护的保护电路，并且包括存储器阵列，其包括多个字线和多个二极管，每个二极管分别耦合在对应的字线和保护电路之间。

35. 发明申请

US20050149664A1 Method for verifying a programmed flash memory 有权
标题翻译：用于验证编程闪存的方法
公开(公告)号：US20050149664A1
公开(公告)日：2005-07-07
申请号：US10962588
申请日：2004-10-13
申请人： Ming-Hung Chou , Hsin-Yi Ho
发明人： Ming-Hung Chou , Hsin-Yi Ho
IPC分类号： G11C11/34 , G11C16/34
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A method for verifying a programmed flash memory. When reading a memory cell, a voltage applied to a drain of the memory cell is a read drain voltage. First, a word line is enabled by applying a verification gate voltage. Next, a first bit line, which is connected to the drain of the memory cell, is enabled and a verification drain voltage, which is higher than the read drain voltage, is applied to the first bit line. Then, a second bit line is enabled and grounded. Thereafter, a third bit line is enabled and a verification isolation voltage is applied. Then, a drain current of the first bit line is sensed, wherein the drain current flows through the first bit line, the memory cell, and the second bit line. Finally, it is judged whether or not the memory cell is successfully programmed according to the drain current.
摘要翻译：一种验证编程闪存的方法。当读取存储单元时，施加到存储单元的漏极的电压是读取漏极电压。首先，通过应用验证门电压来启用字线。接下来，连接到存储单元的漏极的第一位线被使能，并且将高于读取的漏极电压的验证漏极电压施加到第一位线。然后，第二位线被使能并接地。此后，启用第三位线并施加验证隔离电压。然后，感测第一位线的漏极电流，其中漏极电流流过第一位线，存储器单元和第二位线。最后，根据漏极电流判断存储单元是否成功编程。

36. 发明授权

US06599793B2 Memory array with salicide isolation 有权
公开(公告)号：US06599793B2
公开(公告)日：2003-07-29
申请号：US09901888
申请日：2001-05-31
申请人： Ming-Hung Chou , Jui-Lin Lu , Chong-Jen Huang , Shou-Wei Hwang , Hsin-Huei Chen
发明人： Ming-Hung Chou , Jui-Lin Lu , Chong-Jen Huang , Shou-Wei Hwang , Hsin-Huei Chen
IPC分类号： H01L218238
CPC分类号： H01L21/823835 , H01L21/76202 , H01L21/76224
摘要： The present invention provides a memory array fabricated by complementary metal-oxide-semiconductor salicide process. The memory array comprises a semiconductor substrate. Multitudes of first isolation devices are aligned in the semiconductor substrate and second isolation devices aligned on the semiconductor substrate. The alignment of the second isolation devices is parallel to one of the first isolation devices. Some polysilicon lines are on the second isolation devices therefor have null memory function. A conductive structure is below a surface of the semiconductor substrate. The conductive structure is located between the first isolation devices. A conductive contact is on the conductive structure. The correspondence of the first isolation devices and the polysilicon lines can prevent the conductive structures from short effect.

37. 发明授权

US06455896B1 Protection circuit for a memory array 有权
标题翻译：一个存储器阵列的保护电路
公开(公告)号：US06455896B1
公开(公告)日：2002-09-24
申请号：US09840898
申请日：2001-04-25
申请人： Ming-Hung Chou , Chia-Hsing Chen , Smile Huang , Cheng-Jye Liu
发明人： Ming-Hung Chou , Chia-Hsing Chen , Smile Huang , Cheng-Jye Liu
IPC分类号： H01L2362
CPC分类号： H01L27/0255
摘要： The present invention provides a protection circuit comprising one diode wherein the diode is formed by diffusing a heavily doped material of a first conductivity type into a first region of a second conductivity type. An integrated circuit, such as a memory array, is coupled to the diode. The other diode back-to-back is coupled to the diode wherein the other diode is formed by diffusing a heavily doped material of the second conductivity type into the first region and a second region of the first conductivity type. The two diodes in series are capable of discharging for the memory array during manufacturing process.
摘要翻译：本发明提供了一种包括一个二极管的保护电路，其中二极管通过将第一导电类型的重掺杂材料扩散到第二导电类型的第一区域而形成。诸如存储器阵列的集成电路耦合到二极管。另一个二极管背对背耦合到二极管，其中通过将第二导电类型的重掺杂材料扩散到第一区域和第一导电类型的第二区域中而形成另一二极管。串联的两个二极管能够在制造过程中对存储器阵列进行放电。

38. 发明授权

US08867272B2 Method of accessing a non-volatile memory 有权
标题翻译：访问非易失性存储器的方法
公开(公告)号：US08867272B2
公开(公告)日：2014-10-21
申请号：US13556807
申请日：2012-07-24
申请人： Yi Chun Liu , Chung-hsun Lee , Ming Hung Chou
发明人： Yi Chun Liu , Chung-hsun Lee , Ming Hung Chou
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G06F11/1012 , G06F11/1072 , G06F11/186
摘要： A method of accessing a non-volatile memory is disclosed. Original bits of data are duplicated on a bit level to generate a plurality of duplicated bits corresponding to each original bit. At least one shielding bit is provided between the duplicated bits corresponding to different original bits. The duplicated bits and the at least one shielding bit are programmed to the non-volatile memory. The original bits are generated or determined according to the duplicated bits.
摘要翻译：公开了一种访问非易失性存储器的方法。数据的原始位在位电平上复制以产生对应于每个原始位的多个复制位。在对应于不同原始位的复制位之间提供至少一个屏蔽位。复制位和至少一个屏蔽位被编程到非易失性存储器。根据重复的比特生成或确定原始比特。

39. 发明申请

US20120269068A1 TESTING SYSTEM 审中-公开
标题翻译：测试系统
公开(公告)号：US20120269068A1
公开(公告)日：2012-10-25
申请号：US13157634
申请日：2011-06-10
申请人： MING-HUNG CHOU , CHING-FENG HSIEH
发明人： MING-HUNG CHOU , CHING-FENG HSIEH
IPC分类号： H04L12/26 , H04B10/08
CPC分类号： H04L43/50 , H04L43/0811
摘要： A testing system for testing a network apparatus has a plurality of network ports. The system includes a signal generating device for providing a test packet to the network apparatus; a network apparatus connecting device for connecting to the network apparatus; a switching device for switching between a plurality of router lines; and a controlling device for controlling a test procedure, by controlling selection and cycling of the router lines to perform a test on the network ports one by one and allowing the network ports to return the test packet by the test packet return instruction. Accordingly, the network connection status of the network ports of the network apparatus is determined according to the test packet. The test system allows a test to be conducted on the network ports of the network apparatus quickly and at low costs.
摘要翻译：用于测试网络设备的测试系统具有多个网络端口。该系统包括用于向网络设备提供测试分组的信号产生设备; 网络设备连接设备，用于连接到网络设备; 用于在多个路由器线路之间切换的切换装置; 以及用于控制测试过程的控制设备，通过控制路由器线路的选择和循环，逐个对网络端口进行测试，并允许网络端口通过测试分组返回指令返回测试分组。因此，根据测试包确定网络装置的网络端口的网络连接状态。测试系统允许在网络设备的网络端口上以低成本快速进行测试。

40. 发明申请

US20120243310A1 METHOD OF PROGRAMMING A MULTI-BIT PER CELL NON-VOLATILE MEMORY 有权
标题翻译：编程多单元非易失性存储器的方法
公开(公告)号：US20120243310A1
公开(公告)日：2012-09-27
申请号：US13053166
申请日：2011-03-21
申请人： HAN-LUNG HUANG , MING-HUNG CHOU
发明人： HAN-LUNG HUANG , MING-HUNG CHOU
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/26 , G11C16/3454
摘要： A method of programming a multi-bit per cell non-volatile memory is disclosed. In one embodiment, the non-volatile memory is read to obtain a first data of a most-significant-bit (MSB) page on a current word line that succeeds in data reading, wherein the current word line follows a preceding word line on which data reading fails. At least one reference voltage is set. The MSB page on the current word line is secondly programmed with a second data according to the reference voltage, the second data being different from the first data.
摘要翻译：公开了一种编程多位单元非易失性存储器的方法。在一个实施例中，读取非易失性存储器以获得在数据读取中成功的当前字线上的最高有效位（MSB）页的第一数据，其中当前字线遵循之前的字线，数据读取失败。至少设置一个参考电压。当前字线上的MSB页面根据参考电压被第二数据编程，第二数据与第一数据不同。

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