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1. 发明授权

US06599793B2 Memory array with salicide isolation 有权
公开(公告)号：US06599793B2
公开(公告)日：2003-07-29
申请号：US09901888
申请日：2001-05-31
申请人： Ming-Hung Chou , Jui-Lin Lu , Chong-Jen Huang , Shou-Wei Hwang , Hsin-Huei Chen
发明人： Ming-Hung Chou , Jui-Lin Lu , Chong-Jen Huang , Shou-Wei Hwang , Hsin-Huei Chen
IPC分类号： H01L218238
CPC分类号： H01L21/823835 , H01L21/76202 , H01L21/76224
摘要： The present invention provides a memory array fabricated by complementary metal-oxide-semiconductor salicide process. The memory array comprises a semiconductor substrate. Multitudes of first isolation devices are aligned in the semiconductor substrate and second isolation devices aligned on the semiconductor substrate. The alignment of the second isolation devices is parallel to one of the first isolation devices. Some polysilicon lines are on the second isolation devices therefor have null memory function. A conductive structure is below a surface of the semiconductor substrate. The conductive structure is located between the first isolation devices. A conductive contact is on the conductive structure. The correspondence of the first isolation devices and the polysilicon lines can prevent the conductive structures from short effect.

2. 发明授权

US06762089B2 Method for manufacturing a memory device 有权
标题翻译：用于制造存储器件的方法
公开(公告)号：US06762089B2
公开(公告)日：2004-07-13
申请号：US10693092
申请日：2003-10-23
申请人： Kuang-Wen Liu , Chong-Jen Huang , Jui-Lin Lu
发明人： Kuang-Wen Liu , Chong-Jen Huang , Jui-Lin Lu
IPC分类号： H01L218244
CPC分类号： H01L27/112 , H01L23/552 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a memory device including a memory substrate, an insulating layer, a shielding metal layer, a second dielectric layer and a second metal layer. The memory substrate includes a substrate, a memory cell area, a peripheral circuit area, a first dielectric layer and a first metal layer. The first dielectric layer is formed on the memory area and the peripheral circuit area, which are formed on the substrate. The first metal layer is formed on the first dielectric layer while the insulating layer is formed on the first dielectric layer not covered with the first metal layer. The shielding metal layer is formed on the insulating layer over the memory cell area. The second dielectric layer is formed on the shielding metal layer, the insulating layer not covered with the shielding metal layer and the first metal layer not covered with both the shielding layer and the insulating layer. The second metal layer is formed on the second dielectric layer.
摘要翻译：本发明提供了一种存储器件，其包括存储器基板，绝缘层，屏蔽金属层，第二介电层和第二金属层。存储器基板包括基板，存储单元区域，外围电路区域，第一介电层和第一金属层。第一电介质层形成在形成在基板上的存储区域和外围电路区域上。第一金属层形成在第一电介质层上，而绝缘层形成在未被第一金属层覆盖的第一电介质层上。屏蔽金属层形成在存储单元区域上的绝缘层上。第二电介质层形成在屏蔽金属层上，绝缘层未被屏蔽金属层覆盖，第一金属层未被屏蔽层和绝缘层覆盖。第二金属层形成在第二介电层上。

3. 发明授权

US06664586B2 Memory device and manufacturing method thereof 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US06664586B2
公开(公告)日：2003-12-16
申请号：US10193634
申请日：2002-07-10
申请人： Kuang-Wen Liu , Chong-Jen Huang , Jui-Lin Lu
发明人： Kuang-Wen Liu , Chong-Jen Huang , Jui-Lin Lu
IPC分类号： H01L2976
CPC分类号： H01L27/112 , H01L23/552 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a memory device including a memory substrate, an insulating layer, a shielding metal layer, a second dielectric layer and a second metal layer. The memory substrate includes a substrate, a memory cell area, a peripheral circuit area, a first dielectric layer and a first metal layer. The first dielectric layer is formed on the memory area and the peripheral circuit area, which are formed on the substrate. The first metal layer is formed on the first dielectric layer while the insulating layer is formed on the first dielectric layer not covered with the first metal layer. The shielding metal layer is formed on the insulating layer over the memory cell area. The second dielectric layer is formed on the shielding metal layer, the insulating layer not covered with the shielding metal layer and the first metal layer not covered with both the shielding layer and the insulating layer. The second metal layer is formed on the second dielectric layer.
摘要翻译：本发明提供了一种存储器件，其包括存储器基板，绝缘层，屏蔽金属层，第二介电层和第二金属层。存储器基板包括基板，存储单元区域，外围电路区域，第一介电层和第一金属层。第一电介质层形成在形成在基板上的存储区域和外围电路区域上。第一金属层形成在第一电介质层上，而绝缘层形成在未被第一金属层覆盖的第一电介质层上。屏蔽金属层形成在存储单元区域上的绝缘层上。第二电介质层形成在屏蔽金属层上，绝缘层未被屏蔽金属层覆盖，第一金属层未被屏蔽层和绝缘层覆盖。第二金属层形成在第二介电层上。

4. 发明授权

US06800493B2 Pre-erase manufacturing method 有权
标题翻译：预擦除制造方法
公开(公告)号：US06800493B2
公开(公告)日：2004-10-05
申请号：US10026125
申请日：2001-12-20
申请人： Ming-Hung Chou , Smile Huang , Jui-Lin Lu , Tung-Hwang Lin
发明人： Ming-Hung Chou , Smile Huang , Jui-Lin Lu , Tung-Hwang Lin
IPC分类号： H01L2100
CPC分类号： G11C29/50004 , G11C16/04 , G11C16/16 , G11C29/006 , G11C29/50 , H01L21/28273 , H01L21/28282
摘要： The present invention includes methods to pre-erase non-volatile memory cells using an electrical erase signal prior to dividing a wafer into dies. Particular aspects of the present invention are described in the claims, specification and drawings.
摘要翻译：本发明包括在将晶片分成模具之前使用电擦除信号预擦除非易失性存储单元的方法。在权利要求书，说明书和附图中描述了本发明的特定方面。

5. 发明申请

US20050064713A1 [METHOD OF FABRICATING FLASH MEMORY] 有权
标题翻译： [制作闪速存储器的方法]
公开(公告)号：US20050064713A1
公开(公告)日：2005-03-24
申请号：US10605255
申请日：2003-09-18
申请人： Kuang-Chao Chen , Jui-Lin Lu , Ling-Wuu Yang
发明人： Kuang-Chao Chen , Jui-Lin Lu , Ling-Wuu Yang
IPC分类号： H01L21/302 , H01L21/311 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a method of fabricating a flash memory, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on a substrate to form a gate structure. Buried source/drain regions are then formed in the substrate between the strips. The strips are further patterned into floating gate structures. An insulation layer is formed sideways adjacent to the gate structure. The insulation layer has a top surface lower than a top surface of the first conductive layer of the gate structure. The mask layer is removed, and an additional conductive layer is formed on the first conductive layer in a manner to extend over the adjacent insulation layer. The first and additional conductive layers form a floating gate. A gate dielectric layer is formed on the floating gate, and a control gate is formed on the gate dielectric layer.
摘要翻译：在制造闪速存储器的方法中，在衬底上依次形成隧道电介质层，第一导电层和掩模层，以形成栅极结构。然后在条带之间的衬底中形成埋入的源极/漏极区域。条带进一步图案化为浮动栅极结构。绝缘层形成为与栅极结构相邻的侧面。绝缘层具有比栅极结构的第一导电层的顶表面低的顶表面。去除掩模层，并且在第一导电层上形成一个额外的导电层，以便在相邻的绝缘层上延伸。第一和另外的导电层形成浮栅。栅极电介质层形成在浮栅上，在栅介电层上形成控制栅极。

6. 发明申请

US20050064662A1 [METHOD OF FABRICATING FLASH MEMORY] 审中-公开
标题翻译： [制作闪速存储器的方法]
公开(公告)号：US20050064662A1
公开(公告)日：2005-03-24
申请号：US10605254
申请日：2003-09-18
申请人： Ling-Wuu Yang , Kuang-Chao Chen , Jui-Lin Lu
发明人： Ling-Wuu Yang , Kuang-Chao Chen , Jui-Lin Lu
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of fabricating a flash memory. A tunneling dielectric layer, a conductive layer and a mask layer are sequentially formed on a substrate. The mask layer, the conductive layer and the tunneling dielectric layer are patterned to form longitudinally arranged strips on the substrate. Buried drain regions are then formed in the substrate between the strips. The strips are further patterned into floating gate structures. An insulation layer is formed on perimeters of the floating gate structures. The insulation layer has a top surface lower than a top surface of the conductive layer of the floating gate structures, such that a part of sidewalls of the conductive layer is exposed. The mask layer is removed, a gate dielectric layer is formed on the exposed conductive layer, and a control gate is formed on the gate dielectric layer.
摘要翻译：一种制造闪速存储器的方法。在衬底上依次形成隧道电介质层，导电层和掩模层。掩模层，导电层和隧道介电层被图案化以在衬底上形成纵向布置的条带。然后在条带之间的衬底中形成掩埋漏区。条带进一步图案化为浮动栅极结构。在浮栅结构的周边上形成绝缘层。绝缘层具有比浮动栅极结构的导电层的顶表面低的顶表面，使得导电层的侧壁的一部分被暴露。去除掩模层，在暴露的导电层上形成栅极电介质层，并且在栅极介电层上形成控制栅极。

7. 发明授权

US06812096B2 Method for fabrication a flash memory device having self-aligned contact 有权
标题翻译：一种具有自对准接触的闪速存储器件的制造方法
公开(公告)号：US06812096B2
公开(公告)日：2004-11-02
申请号：US10248713
申请日：2003-02-12
申请人： Kuang-Chao Chen , Ling-Wuu Yang , Jui-Lin Lu
发明人： Kuang-Chao Chen , Ling-Wuu Yang , Jui-Lin Lu
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76897 , H01L27/115
摘要： A flash memory device that comprises a self-aligned contact opening and a fabrication method thereof are described. Subsequent to the formation of the control gate of the flash memory device, a spacer is formed over a sidewall of the gate layer in a subsequent process, followed by forming another dielectric layer over the substrate to cover the control gate. Thereafter, the dielectric layer and the dielectric layer underlying the control gate are patterned to form a self-aligned contact opening between two neighboring control gates to expose a bit line in the substrate. A conductive material further fills the self-aligned contact opening.
摘要翻译：描述了包括自对准接触开口的闪存器件及其制造方法。在闪存器件的控制栅极形成之后，在随后的工艺中在栅极层的侧壁上形成间隔物，随后在衬底上形成覆盖控制栅极的另一介电层。此后，将电介质层和位于控制栅极下面的电介质层图案化以在两个相邻的控制栅极之间形成自对准的接触开口，以暴露衬底中的位线。导电材料还填充自对准的接触开口。

8. 发明授权

US06943118B2 Method of fabricating flash memory 有权
标题翻译：制造闪存的方法
公开(公告)号：US06943118B2
公开(公告)日：2005-09-13
申请号：US10605255
申请日：2003-09-18
申请人： Kuang-Chao Chen , Jui-Lin Lu , Ling-Wuu Yang
发明人： Kuang-Chao Chen , Jui-Lin Lu , Ling-Wuu Yang
IPC分类号： H01L21/302 , H01L21/311 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a method of fabricating a flash memory, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on a substrate to form a gate structure. Buried source/drain regions are then formed in the substrate between the strips. The strips are further patterned into floating gate structures. An insulation layer is formed sideways adjacent to the gate structure. The insulation layer has a top surface lower than a top surface of the first conductive layer of the gate structure. The mask layer is removed, and an additional conductive layer is formed on the first conductive layer in a manner to extend over the adjacent insulation layer. The first and additional conductive layers form a floating gate. A gate dielectric layer is formed on the floating gate, and a control gate is formed on the gate dielectric layer.
摘要翻译：在制造闪速存储器的方法中，在衬底上依次形成隧道电介质层，第一导电层和掩模层，以形成栅极结构。然后在条带之间的衬底中形成埋入的源极/漏极区域。条带进一步图案化为浮动栅极结构。绝缘层形成为与栅极结构相邻的侧面。绝缘层具有比栅极结构的第一导电层的顶表面低的顶表面。去除掩模层，并且在第一导电层上形成一个额外的导电层，以便在相邻的绝缘层上延伸。第一和另外的导电层形成浮栅。栅极电介质层形成在浮栅上，在栅介电层上形成控制栅极。

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