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1. 发明授权

US07251166B2 Method for verifying a programmed flash memory 有权
标题翻译：用于验证编程闪存的方法
公开(公告)号：US07251166B2
公开(公告)日：2007-07-31
申请号：US10962588
申请日：2004-10-13
申请人： Ming-Hung Chou , Hsin-Yi Ho
发明人： Ming-Hung Chou , Hsin-Yi Ho
IPC分类号： G11C11/34
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A method for verifying a programmed flash memory. When reading a memory cell, a voltage applied to a drain of the memory cell is a read drain voltage. First, a word line is enabled by applying a verification gate voltage. Next, a first bit line, which is connected to the drain of the memory cell, is enabled and a verification drain voltage, which is higher than the read drain voltage, is applied to the first bit line. Then, a second bit line is enabled and grounded. Thereafter, a third bit line is enabled and a verification isolation voltage is applied. Then, a drain current of the first bit line is sensed, wherein the drain current flows through the first bit line, the memory cell, and the second bit line. Finally, it is judged whether or not the memory cell is successfully programmed according to the drain current.
摘要翻译：一种验证编程闪存的方法。当读取存储单元时，施加到存储单元的漏极的电压是读取漏极电压。首先，通过应用验证门电压来启用字线。接下来，连接到存储单元的漏极的第一位线被使能，并且将高于读取的漏极电压的验证漏极电压施加到第一位线。然后，第二位线被使能并接地。此后，启用第三位线并施加验证隔离电压。然后，感测第一位线的漏极电流，其中漏极电流流过第一位线，存储器单元和第二位线。最后，根据漏极电流判断存储单元是否成功编程。

2. 发明授权

US06545911B2 Flash memory erase method 有权
公开(公告)号：US06545911B2
公开(公告)日：2003-04-08
申请号：US09930801
申请日：2001-08-14
申请人： Ming-Hung Chou , Hsin-Yi Ho , Smile Huang
发明人： Ming-Hung Chou , Hsin-Yi Ho , Smile Huang
IPC分类号： G11C1604
CPC分类号： G11C16/3468 , G11C16/344
摘要： An flash memory erase method. A bias Vg is applied to a gate of a memory cell. A bias Vd is applied to a source/drain region of the memory cell to execute an erase operation. The bias Vd is increased from an initial value to a predetermined value over time. During the increase of the bias Vd, no inspection is performed. Whether the memory of each memory cell has been erased is inspected. If the erase operation is complete, the erase operation is over. If not, a voltage raise erase-inspection step is performed at least once until it is confirmed that the memory of all the memory cells has been erase. Each voltage raise erase-inspection step includes an erase step with a raised voltage and an inspection step afterwards.

3. 发明申请

US20050149664A1 Method for verifying a programmed flash memory 有权
标题翻译：用于验证编程闪存的方法
公开(公告)号：US20050149664A1
公开(公告)日：2005-07-07
申请号：US10962588
申请日：2004-10-13
申请人： Ming-Hung Chou , Hsin-Yi Ho
发明人： Ming-Hung Chou , Hsin-Yi Ho
IPC分类号： G11C11/34 , G11C16/34
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A method for verifying a programmed flash memory. When reading a memory cell, a voltage applied to a drain of the memory cell is a read drain voltage. First, a word line is enabled by applying a verification gate voltage. Next, a first bit line, which is connected to the drain of the memory cell, is enabled and a verification drain voltage, which is higher than the read drain voltage, is applied to the first bit line. Then, a second bit line is enabled and grounded. Thereafter, a third bit line is enabled and a verification isolation voltage is applied. Then, a drain current of the first bit line is sensed, wherein the drain current flows through the first bit line, the memory cell, and the second bit line. Finally, it is judged whether or not the memory cell is successfully programmed according to the drain current.
摘要翻译：一种验证编程闪存的方法。当读取存储单元时，施加到存储单元的漏极的电压是读取漏极电压。首先，通过应用验证门电压来启用字线。接下来，连接到存储单元的漏极的第一位线被使能，并且将高于读取的漏极电压的验证漏极电压施加到第一位线。然后，第二位线被使能并接地。此后，启用第三位线并施加验证隔离电压。然后，感测第一位线的漏极电流，其中漏极电流流过第一位线，存储器单元和第二位线。最后，根据漏极电流判断存储单元是否成功编程。

4. 发明授权

US08194462B2 Integrated circuit of device for memory cell 有权
标题翻译：用于存储单元的器件集成电路
公开(公告)号：US08194462B2
公开(公告)日：2012-06-05
申请号：US13209241
申请日：2011-08-12
申请人： Hsin-Yi Ho , Ji-Yu Hung
发明人： Hsin-Yi Ho , Ji-Yu Hung
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/3418 , G11C16/3427
摘要： A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages.
摘要翻译：多级单元（MLC）存储器的读取方法包括以下步骤。多个字线电压依次提供给MLC存储单元。对应于字线电压的多个位线电压被依次提供给MLC存储单元。字线电压之一高于另一个字线电压，并且与字线电压中的一个相对应的位线电压之一低于对应于另一个字线电压的另一个位线电压字线电压。

5. 发明申请

US20100039304A1 DIGITAL TO ANALOG CONVERTER AND METHOD THEREOF 有权
标题翻译：数字到模拟转换器及其方法
公开(公告)号：US20100039304A1
公开(公告)日：2010-02-18
申请号：US12338633
申请日：2008-12-18
申请人： Jer-Hau Hsu , Tien-Yen Wang , Hsin-Yi Ho
发明人： Jer-Hau Hsu , Tien-Yen Wang , Hsin-Yi Ho
IPC分类号： H03M1/78
CPC分类号： H03M1/808
摘要： A digital to analog converter (DAC) has a plurality of transistor-resistor units connected in a string. Each of the transistor-resistor units of the DAC has a pair of transistors that are turned on/off by a pair of complementary control signals. Since the two transistors of each transistor-resistor unit are positioned symmetrically, an equivalent resistance would be determined precisely according to received digital codes, such that an output voltage of the DAC could be adjusted precisely based on the equivalent resistance.
摘要翻译：数模转换器（DAC）具有串联连接的多个晶体管电阻单元。 DAC的每个晶体管 - 电阻单元都有一对晶体管，通过一对互补控制信号导通/截止。由于每个晶体管 - 电阻器单元的两个晶体管对称地定位，所以根据接收到的数字代码精确地确定等效电阻，使得可以基于等效电阻精确地调整DAC的输出电压。

6. 发明授权

US07961513B2 Method for programming a multilevel memory 有权
标题翻译：多级存储器编程方法
公开(公告)号：US07961513B2
公开(公告)日：2011-06-14
申请号：US12544025
申请日：2009-08-19
申请人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
发明人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5671 , G11C2211/5621
摘要： A method for programming a MLC memory includes (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL−K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.
摘要翻译：用于编程MLC存储器的方法包括（a）通过使用Vd偏置BL将具有低于目标编程状态的PV电平的Vt电平的存储器的位编程为编程位; （b）如果存储器的每个位的Vt电平不低于目标编程状态的PV电平，则结束该方法，否则继续步骤（c）; 以及（c）设定BL = BL + K1，并且如果每个编程的比特都具有低于PV水平的Vt级别，而设置BL = BL-K2，并重复步骤（a），如果在至少一个编程位的Vt电平不低于PV电平。

7. 发明申请

US20110085378A1 Memory and Operation Method Therefor 有权
标题翻译：记忆及其操作方法
公开(公告)号：US20110085378A1
公开(公告)日：2011-04-14
申请号：US12576323
申请日：2009-10-09
申请人： Hsin-Yi Ho , Chun-Hsiung Hung , Yun-Chen Chou
发明人： Hsin-Yi Ho , Chun-Hsiung Hung , Yun-Chen Chou
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5642 , G11C16/26 , G11C16/349
摘要： In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second reading is performed on the memory cells by applying the moved reference voltage; a first total number of a first logic state in the first reading is compared with a second total number of the first logic state in the second reading if it is checked that the second reading result is not correct; and the moving of the reference voltage is stopped if the first reading result has the same number of the first logic state as the second reading result, and the moved reference voltage is stored as a target reference voltage.
摘要翻译：在包括多个存储单元的存储器的操作方法中，通过施加参考电压对存储器单元执行第一读取; 如果检查到第一读取结果不正确，则移动参考电压; 通过施加移动的参考电压对存储器单元执行第二读取; 如果检查到第二读取结果不正确，则将第一读取中的第一逻辑状态的第一总数与第二读取中的第一逻辑状态的第二总数进行比较; 并且如果第一读取结果具有与第二读取结果相同数量的第一逻辑状态，并且移动的参考电压被存储为目标参考电压，则参考电压的移动停止。

8. 发明申请

US20110058414A1 MEMORY WITH MULTIPLE REFERENCE CELLS 有权
标题翻译：具有多个参考电池的存储器
公开(公告)号：US20110058414A1
公开(公告)日：2011-03-10
申请号：US12555872
申请日：2009-09-09
申请人： Hsin-Yi Ho , Chia-Ching Li
发明人： Hsin-Yi Ho , Chia-Ching Li
IPC分类号： G11C16/04 , G11C16/06 , G11C7/02
CPC分类号： G11C7/04 , G11C11/56 , G11C11/5642 , G11C2211/5634
摘要： A memory includes a memory array, a sense amplifier, and a reference circuit. The memory array includes a memory cell. The sense amplifier includes a first terminal coupled to the memory cell and a second terminal. The reference circuit includes a first reference cell, a second reference cell, and a switch. The first reference cell has a first reference threshold voltage for providing a first reference current, based on a first reference word line voltage. The second reference cell has a second reference threshold voltage for providing a second reference current, based on a second reference word line voltage. The switch selectively provides one of the first and the second reference currents to the second terminal in response to a control signal. The first and the second reference word line voltages correspond to different voltage levels.
摘要翻译：存储器包括存储器阵列，读出放大器和参考电路。存储器阵列包括存储器单元。读出放大器包括耦合到存储单元的第一端子和第二端子。参考电路包括第一参考单元，第二参考单元和开关。第一参考单元具有用于基于第一参考字线电压提供第一参考电流的第一参考阈值电压。第二参考单元具有第二参考阈值电压，用于基于第二参考字线电压提供第二参考电流。响应于控制信号，开关选择性地将第一和第二参考电流中的一个提供给第二端子。第一和第二参考字线电压对应于不同的电压电平。

9. 发明申请

US20110055670A1 Programming Method and Memory Device Using the Same 有权
标题翻译：编程方法和使用它的存储设备
公开(公告)号：US20110055670A1
公开(公告)日：2011-03-03
申请号：US12943443
申请日：2010-11-10
申请人： Chun-Hsiung Hung , Hsin-Yi Ho
发明人： Chun-Hsiung Hung , Hsin-Yi Ho
IPC分类号： G11C11/40 , G11C7/00 , G06F11/07
CPC分类号： G11C16/3404 , G11C16/3454
摘要： A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming command.
摘要翻译：提供了一种应用于存储器的编程方法。存储器包括多个存储单元。该方法包括以下步骤。响应于第一编程命令对存储器单元的目标单元进行编程。响应于第二编程命令对目标单元进行编程。

10. 发明授权

US07580292B2 Method for programming a multilevel memory 有权
标题翻译：多级存储器编程方法
公开(公告)号：US07580292B2
公开(公告)日：2009-08-25
申请号：US11812033
申请日：2007-06-14
申请人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
发明人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5671 , G11C2211/5621
摘要： A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method includes (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL−K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.
摘要翻译：提供了一种用于编程MLC存储器的方法。 MLC存储器有多个位，每个位都有多个编程状态。每个编程状态具有第一PV级别。该方法包括（a）通过使用Vd偏置BL将具有低于目标编程状态的PV电平的Vt电平的存储器的位编程为编程位; （b）如果存储器的每个位的Vt电平不低于目标编程状态的PV电平，则结束该方法，否则继续步骤（c）; 以及（c）设定BL = BL + K1，并且如果每个编程的比特都具有低于PV水平的Vt级别，而设置BL = BL-K2，并重复步骤（a），如果在至少一个编程位的Vt电平不低于PV电平。

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