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31. 发明授权

US07968460B2 Semiconductor with through-substrate interconnect 有权
标题翻译：半导体与通孔基板互连
公开(公告)号：US07968460B2
公开(公告)日：2011-06-28
申请号：US12142251
申请日：2008-06-19
申请人： Kyle Kirby , Kunal Parekh
发明人： Kyle Kirby , Kunal Parekh
IPC分类号： H01L21/44
CPC分类号： H01L21/743 , H01L21/26513 , H01L21/76802 , H01L21/76831 , H01L21/76877 , H01L21/76895 , H01L21/76898 , H01L21/823475 , H01L23/481 , H01L23/49816 , H01L27/0694 , H01L27/10888 , H01L27/10894 , H01L29/66568 , H01L29/78 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548
摘要： Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.
摘要翻译：描述了具有垂直延伸穿过器件的一部分到半导体衬底背面的金属互连的半导体器件。金属互连的顶部区域垂直位于包含金属布线层的水平平面的下方。制造半导体器件的方法可以包括将通孔蚀刻到半导体衬底中，用金属材料填充通孔，在填充通孔之后形成金属布线层，以及去除半导体衬底的底部的一部分以露出底部金属填充通孔的区域。

32. 发明申请

US20080119053A1 METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE, AND DEVICE COMPRISING SAME 有权
标题翻译：在存储器件上制造隔板间隔的方法以及包含其的装置
公开(公告)号：US20080119053A1
公开(公告)日：2008-05-22
申请号：US12020752
申请日：2008-01-28
申请人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
发明人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
IPC分类号： H01L21/311
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11543
摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.
摘要翻译：本发明一般涉及在存储器件上制造侧壁间隔物的方法，以及包括这种侧壁间隔物的存储器件。在一个说明性实施例中，该方法包括在由存储器阵列和至少一个外围电路构成的存储器件上形成侧壁间隔物，该隔离物通过形成邻近存储器阵列中的字线结构的第一侧壁间隔物，第一侧壁间隔物具有第一厚度以及在所述外围电路中形成与所述晶体管结构相邻的第二侧壁间隔物，所述第二侧壁间隔物具有大于所述第一厚度的第二厚度，其中所述第一和第二侧壁间隔物包括来自单层间隔物材料的材料。在一个说明性实施例中，该装置包括由多个字线结构组成的存储器阵列，多个字线结构中的每一个具有与其相邻形成的第一侧壁间隔物，第一侧壁间隔物具有第一厚度，外围电路包括至少一个晶体管，其具有与其相邻形成的第二侧壁间隔物，所述第二侧壁间隔物具有大于第一厚度的第二厚度，所述第一和第二侧壁间隔物由来自单层间隔物材料的材料构成。

33. 发明申请

US20070141821A1 Method of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors 有权
标题翻译：形成集成电路的方法，形成存储器电路的方法以及形成场效应晶体管的方法
公开(公告)号：US20070141821A1
公开(公告)日：2007-06-21
申请号：US11704488
申请日：2007-02-09
申请人： Kunal Parekh , John Zahurak
发明人： Kunal Parekh , John Zahurak
IPC分类号： H01L21/44
CPC分类号： H01L21/823468 , H01L21/823418 , H01L21/823425 , H01L27/105 , H01L27/11526 , H01L27/11534
摘要： The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.
摘要翻译：本发明包括形成集成电路的方法，形成存储器电路的方法以及形成场效应晶体管的方法。在一个实施方案中，导电金属硅化物形成在衬底的一些区域上而不是其它区域上。在一个实施方案中，导电金属硅化物形成在晶体管源极/漏极区上，并且与在晶体管的栅极附近的各向异性蚀刻的侧壁间隔开。

34. 发明申请

US20070004132A1 DRAM memory device 有权
标题翻译： DRAM存储器件
公开(公告)号：US20070004132A1
公开(公告)日：2007-01-04
申请号：US11515648
申请日：2006-09-05
申请人： Kunal Parekh , Byron Burgess
发明人： Kunal Parekh , Byron Burgess
IPC分类号： H01L21/8242
CPC分类号： H01L21/76897 , H01L21/76831 , H01L21/76834 , H01L21/76895 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L27/10894 , Y10S257/905 , Y10S257/906 , Y10S257/907
摘要： The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.
摘要翻译：本发明包括形成存储器电路的方法。在一个实施方案中，半导体衬底包括一对在其间接收的位节点的字线。在位节点上的绝缘材料内形成位节点接触开口。牺牲性封堵材料形成在一对字线之间的位节点接触开口内。牺牲性封堵材料从一对字线对之间的位节点接触开口移除，并由与位节点电连接的导电材料代替。之后，将导电材料形成为位线。

35. 发明申请

US20060263987A1 Methods of forming fusible devices 审中-公开
标题翻译：形成易熔装置的方法
公开(公告)号：US20060263987A1
公开(公告)日：2006-11-23
申请号：US11496251
申请日：2006-07-31
申请人： Mark Fischer , Zhiping Yin , Thomas Glass , Kunal Parekh , Gurtej Sandhu
发明人： Mark Fischer , Zhiping Yin , Thomas Glass , Kunal Parekh , Gurtej Sandhu
IPC分类号： H01L21/336
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. The fuse also includes an outer insulating element that overlays and encloses the heat conductive element and the absorption element.
摘要翻译：本发明涉及一种激光熔丝。激光熔丝包括包含导热材料的元件。保险丝还包括吸收元件，该吸收元件包括具有与热传导元件重叠的热或光吸收的可调容量的材料。保险丝还包括覆盖并包围导热元件和吸收元件的外绝缘元件。

36. 发明申请

US20060234469A1 A method of forming semiconductor structures 审中-公开
标题翻译：一种形成半导体结构的方法
公开(公告)号：US20060234469A1
公开(公告)日：2006-10-19
申请号：US11409134
申请日：2006-04-21
申请人： David Dickerson , Richard Lane , Charles Dennison , Kunal Parekh , Mark Fischer , John Zahurak
发明人： David Dickerson , Richard Lane , Charles Dennison , Kunal Parekh , Mark Fischer , John Zahurak
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.
摘要翻译：一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

37. 发明申请

US20060231528A1 Methods of forming semiconductor constructions 有权
公开(公告)号：US20060231528A1
公开(公告)日：2006-10-19
申请号：US11455023
申请日：2006-06-15
申请人： Werner Juengling , Steven McDonald , Kunal Parekh
发明人： Werner Juengling , Steven McDonald , Kunal Parekh
IPC分类号： B44C1/22 , C23F1/00 , H01L21/461 , H01L21/302
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication and patterning of bond pads and redistribution layers is conducted simultaneously over a fuse box region to form and/or remove materials that are directly over the fuse box region.

38. 发明申请

US20060046355A1 Methods of forming semiconductor constructions 有权
公开(公告)号：US20060046355A1
公开(公告)日：2006-03-02
申请号：US10925793
申请日：2004-08-24
申请人： Kunal Parekh , Chandra Mouli , M. Roberts , Fernando Gonzalez
发明人： Kunal Parekh , Chandra Mouli , M. Roberts , Fernando Gonzalez
IPC分类号： H01L21/00 , H01L21/84 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L21/823462 , H01L21/823481 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/785
摘要： The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.

39. 发明授权

US06787839B2 Capacitor structure 有权
公开(公告)号：US06787839B2
公开(公告)日：2004-09-07
申请号：US10145435
申请日：2002-05-14
申请人： Zhiqiang Wu , Kunal Parekh , Li Li
发明人： Zhiqiang Wu , Kunal Parekh , Li Li
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L28/82
摘要： The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.

40. 发明授权

US06756627B1 Container capacitor 失效
标题翻译：集装箱电容器
公开(公告)号：US06756627B1
公开(公告)日：2004-06-29
申请号：US09033290
申请日：1998-03-02
申请人： Zhiquiang Wu , Li Li , Kunal Parekh
发明人： Zhiquiang Wu , Li Li , Kunal Parekh
IPC分类号： H01L27108
CPC分类号： H01L27/1085 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/90
摘要： A method of the present invention forms a vertically oriented structure connected with a source/drain region through open space. In one embodiment of the method wherein a capacitor storage node is formed, the open space is located between two word line gate stacks in a MOS DRAM memory circuit. A thin landing pad is formed of conducting material in the open space extending to the source/drain region and over the tops of the gate stacks. An insulating layer is formed over the gate stacks and the landing pad. A recess is etched down through the insulating layer to expose an annular portion of the landing pad. A volume of the insulating material is left upon the landing pad in the open space. A conductive layer is deposited in the recess making contact with the exposed annular portion of the landing pad. A dry etching process is used to remove a segment of the conductive layer formed over the volume of insulating material upon the landing pad, after which the volume of insulating material upon the landing pad is removed. Remaining is a storage node made upon of a continuous layer of conductive material that lines the recess and the open space. A dielectric layer and a cell plate are in one embodiment formed over the continuous layer of conducting material so as to extend down into the open space, thus completing a container capacitor.
摘要翻译：本发明的方法形成了通过开放空间与源/漏区连接的垂直定向结构。在其中形成电容器存储节点的方法的一个实施例中，开放空间位于MOS DRAM存储器电路中的两个字线栅极叠层之间。薄的着陆板由导电材料形成，该导电材料在延伸到源极/漏极区域以及栅极堆叠顶部的开放空间中。绝缘层形成在栅极叠层和着陆焊盘上。通过绝缘层向下蚀刻凹陷以暴露着陆垫的环形部分。绝缘材料的体积留在开放空间中的着陆垫上。导电层沉积在与着陆焊盘暴露的环形部分接触的凹部中。使用干蚀刻工艺去除在着陆焊盘上形成在绝缘材料体积上的导电层的段，之后移除着陆焊盘上的绝缘材料的体积。剩余的是由连续的导电材料层制成的存储节点，其导引凹槽和开放空间。在一个实施例中，在导电材料的连续层上形成电介质层和电池板，以便向下延伸到开放空间中，从而完成容器电容器。

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