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    • 4. 发明授权
    • Capacitor structure
    • 电容结构
    • US06740923B2
    • 2004-05-25
    • US10145250
    • 2002-05-14
    • Zhiqiang WuKunal ParekhLi Li
    • Zhiqiang WuKunal ParekhLi Li
    • H01L31119
    • H01L27/10852H01L28/82
    • The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.
    • 本发明涉及一种电容器的制造,该电容器形成为具有大致凹入形状且具有可选择的折叠或回旋表面。 凹形形状在小体积内优化表面积,从而使电容器能够保持大量电荷,从而有助于微电子领域中的增加的小型化努力。 电容器以与电致密DRAM阵列一致的微电子方式制造。 制造方法包括具有在半导体衬底表面上方延伸的存储节点的堆叠构造。
    • 5. 发明授权
    • Method of making a concave capacitor
    • 制作凹电容器的方法
    • US06682984B1
    • 2004-01-27
    • US09535483
    • 2000-03-24
    • Zhiqiang WuKunal ParekhLi Li
    • Zhiqiang WuKunal ParekhLi Li
    • H01L2120
    • H01L27/10852H01L28/82
    • The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.
    • 本发明涉及一种电容器的制造,该电容器形成为具有大致凹入形状且具有可选择的折叠或回旋表面。 凹形形状在小体积内优化表面积,从而使电容器能够保持大量电荷,从而有助于微电子领域中的增加的小型化努力。 电容器以与电致密DRAM阵列一致的微电子方式制造。 制造方法包括具有在半导体衬底表面上方延伸的存储节点的堆叠构造。
    • 6. 发明授权
    • Method of making a capacitor
    • 制作电容器的方法
    • US5786250A
    • 1998-07-28
    • US818597
    • 1997-03-14
    • Zhiqiang WuLi LiKunal Parekh
    • Zhiqiang WuLi LiKunal Parekh
    • H01L21/02H01L21/8242H01L27/108
    • H01L27/1085H01L27/10817H01L28/82H01L28/84H01L28/90
    • A method of the present invention forms a vertically oriented structure connected with a source/drain region through an open space. In one embodiment of the method wherein a capacitor storage node is formed, the open space is located between two word line gate stacks in a MOS DRAM memory circuit. A thin landing pad is formed of conducting material in the open space extending to the source/drain region and over the tops of the gate stacks. An insulating layer is formed over the gate stacks and the landing pad. A recess is etched down through the insulating layer to expose an annular portion of the landing pad. A volume of the insulating material is left upon the landing pad in the open space. A conductive layer is deposited in the recess making contact with the exposed annular portion of the landing pad. A dry etching process is used to remove a segment of the conductive layer formed over the volume of insulating material upon the landing pad, after which the volume of insulating material upon the landing pad is removed. Remaining is a storage node made upon of a continuous layer of conductive material that lines the recess and the open space. A dielectric layer and a cell plate are in one embodiment formed over the continuous layer of conducting material so as to extend down into the open space, thus completing a container capacitor.
    • 本发明的方法形成了通过开放空间与源极/漏极区域连接的垂直取向结构。 在其中形成电容器存储节点的方法的一个实施例中,开放空间位于MOS DRAM存储器电路中的两个字线栅极叠层之间。 薄的着陆板由导电材料形成,该导电材料在延伸到源极/漏极区域以及栅极堆叠顶部的开放空间中。 绝缘层形成在栅极叠层和着陆焊盘上。 通过绝缘层向下蚀刻凹陷以暴露着陆垫的环形部分。 绝缘材料的体积留在开放空间中的着陆垫上。 导电层沉积在与着陆焊盘暴露的环形部分接触的凹部中。 使用干蚀刻工艺去除在着陆焊盘上形成在绝缘材料体积上的导电层的段,之后移除着陆焊盘上的绝缘材料的体积。 剩余的是由连续的导电材料层制成的存储节点,其导引凹槽和开放空间。 在一个实施例中,在导电材料的连续层上形成电介质层和电池板,以便向下延伸到开放空间中,从而完成容器电容器。
    • 9. 发明授权
    • Methods of making implanted structures
    • 植入结构的方法
    • US06309975B1
    • 2001-10-30
    • US08818660
    • 1997-03-14
    • Zhiqiang WuLi LiThomas A. FiguraKunal R. ParekhPai-Hung PanAlan R. ReinbergKin F. Ma
    • Zhiqiang WuLi LiThomas A. FiguraKunal R. ParekhPai-Hung PanAlan R. ReinbergKin F. Ma
    • H01L2100
    • H01L27/10852H01L21/2815H01L21/28525H01L21/30608H01L21/32134H01L21/76232H01L21/76237H01L21/7624H01L21/76838H01L21/76897H01L27/10817H01L28/60H01L29/66492H01L29/66575
    • Methods are disclosed for forming shaped structures of silicon-containing material with ion implantation and an etching process which is selective to silicon-containing material implanted to a certain concentration of ions or with an etching process which is selective to relatively unimplanted silicon-containing material. In general, the methods initially involve providing a layer of silicon-containing material such as polysilicon or epitaxial silicon on a semiconductor substrate. The layer of silicon-containing material is then masked, and ions are implanted into exposed portions of the layer of silicon-containing material. The mask is removed, and the aforementioned selective etching process is conducted to result in one of an implanted and a relatively unimplanted portion of the layer of silicon-containing material being etched away and the other left standing to form a shaped structure of silicon-containing material. One preferred selective etching process uses an etchant solution comprising a selected weight percentage of tetramethyl ammonium hydroxide in deionized water. The etchant solution etches relatively unimplanted silicon-containing material implanted up to 60 times faster than it etches silicon-containing material implanted to beyond a threshold concentration of ions. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.
    • 公开了用于通过离子注入形成含硅材料的成形结构的方法,以及对注入一定浓度的离子的含硅材料或对相对未被植入的含硅材料选择性的蚀刻工艺是选择性的蚀刻工艺。 通常,该方法最初涉及在半导体衬底上提供诸如多晶硅或外延硅的含硅材料层。 然后掩蔽含硅材料层,并将离子注入含硅材料层的暴露部分。 去除掩模,并且进行上述选择性蚀刻工艺以导致被蚀刻掉的含硅材料层的注入和相对未被注入的部分中的一个,而另一个放置形成含硅的成形结构 材料。 一种优选的选择性蚀刻方法使用包含选定重量百分比的四甲基氢氧化铵在去离子水中的蚀刻剂溶液。 蚀刻剂溶液蚀刻相对未被植入的含硅材料,其比注入超过阈值浓度离子的含硅材料蚀刻高达60倍。 各种方法用于形成凸起形状的结构,成形开口,多晶硅插塞,电容器存储节点,环绕栅极晶体管,独立壁,互连线,沟槽电容器和沟槽隔离区域。