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31. 发明申请

US20110222342A1 DATA STORAGE SYSTEM HAVING MULTI-BIT MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
标题翻译：具有多位存储器件的数据存储系统及其操作方法
公开(公告)号：US20110222342A1
公开(公告)日：2011-09-15
申请号：US13040295
申请日：2011-03-04
申请人： Sangyong Yoon , Kitae Park , Jinman Han , Wonseok Lee
发明人： Sangyong Yoon , Kitae Park , Jinman Han , Wonseok Lee
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5628 , G11C14/0018 , G11C16/0483 , G11C16/26 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory and which controls the non-volatile memory device. The operating method of the data storage device includes storing data in the buffer memory according to an external request, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the determined program pattern.
摘要翻译：数据存储装置包括：非易失性存储装置，其包括存储单元阵列; 以及包括缓冲存储器并且控制非易失性存储器件的存储器控制器。数据存储装置的操作方法包括根据外部请求将数据存储在缓冲存储器中，并且确定存储在缓冲存储器中的数据是否是与存储单元阵列的缓冲器程序操作相关的数据。当存储在缓冲存储器中的数据是伴随缓冲器程序操作的数据时，该方法还包括确定是否需要对存储单元阵列执行主程序操作，并且当需要存储单元阵列的主程序操作时，存储单元阵列中的主程序操作的程序模式。该方法还包括基于所确定的程序模式向存储器单元阵列发出用于主程序操作的一组命令给多位存储器件。

32. 发明申请

US20100039861A1 NONVOLATILE MEMORY DEVICE AND READ METHOD 有权
标题翻译：非易失性存储器件和读取方法
公开(公告)号：US20100039861A1
公开(公告)日：2010-02-18
申请号：US12506345
申请日：2009-07-21
申请人： Kitae Park , Myoung Gon Kang
发明人： Kitae Park , Myoung Gon Kang
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： Disclosed is a nonvolatile memory including a memory cell array including a first cell string connected between a first bit line and a first common source line, and a second cell string a second common source line and a second bit line adjacent to the first bit line. The nonvolatile memory also includes a control logic circuit configured to independently control the first and second common source lines.
摘要翻译：公开了一种非易失性存储器，包括存储单元阵列，其包括连接在第一位线和第一公共源极线之间的第一单元串，以及第二单元串，与第一位线相邻的第二公共源极线和第二位线。非易失性存储器还包括被配置为独立地控制第一和第二公共源极线的控制逻辑电路。

33. 发明申请

US20100020611A1 FLASH MEMORY SYSTEMS AND OPERATING METHODS USING ADAPTIVE READ VOLTAGE LEVELS 有权
标题翻译：使用自适应读取电压水平的闪存存储器系统和操作方法
公开(公告)号：US20100020611A1
公开(公告)日：2010-01-28
申请号：US12490896
申请日：2009-06-24
申请人： Kitae Park
发明人： Kitae Park
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/28 , G11C16/3418 , G11C16/3431 , G11C29/00 , G11C2211/5634
摘要： Some embodiments of the present invention provide methods of operating nonvolatile memory devices. Reference data is stored in a plurality of memory cells. The reference data is read, and a threshold voltage distribution of the plurality of memory cells is determined responsive to reading the reference data. A read voltage of the nonvolatile memory device is modified based on the determined threshold voltage distribution. The nonvolatile memory device may include a main region configured to stored data and a dummy region configured to store the reference data, and the methods may further include reading data from the main region using the modified read voltage.
摘要翻译：本发明的一些实施例提供了操作非易失性存储器件的方法。参考数据存储在多个存储单元中。读取参考数据，并且响应于读取参考数据确定多个存储器单元的阈值电压分布。基于确定的阈值电压分布来修改非易失性存储器件的读取电压。非易失性存储器件可以包括被配置为存储数据的主区域和被配置为存储参考数据的虚拟区域，并且所述方法还可以包括使用修改的读取电压从主区域读取数据。

34. 发明申请

US20090316491A1 NON-VOLATILE MEMORY DEVICES AND METHODS OF ERASING NON-VOLATILE MEMORY DEVICES 有权
标题翻译：非易失性存储器件和消除非易失性存储器件的方法
公开(公告)号：US20090316491A1
公开(公告)日：2009-12-24
申请号：US12486056
申请日：2009-06-17
申请人： Kitae PARK , Doogon Kim , Moosung Kim , Hansoo Kim
发明人： Kitae PARK , Doogon Kim , Moosung Kim , Hansoo Kim
IPC分类号： G11C16/04 , G11C7/06
CPC分类号： G11C16/0483 , G11C16/16
摘要： In one embodiment, an erase method for a memory including a memory array having at least first and second programmable transistors connected in series, includes restricting flow of electrons from the first programmable transistor into the second programmable transistor during an erase operation.
摘要翻译：在一个实施例中，包括具有串联连接的至少第一和第二可编程晶体管的存储器阵列的存储器的擦除方法包括在擦除操作期间限制电子从第一可编程晶体管流入第二可编程晶体管。

35. 发明申请

US20220102750A1 LITHIUM BATTERY 有权
公开(公告)号：US20220102750A1
公开(公告)日：2022-03-31
申请号：US17545036
申请日：2021-12-08
申请人： Hyeokjo Gwon , Jinkju Kang , Kitae Park , Hyunchul Lee , Ryounghee Kim , Euncheol Do , Soojin Park , Sangmin Ji
发明人： Hyeokjo Gwon , Jinkju Kang , Kitae Park , Hyunchul Lee , Ryounghee Kim , Euncheol Do , Soojin Park , Sangmin Ji
IPC分类号： H01M10/052 , H01M10/0567 , H01M50/44 , H01M50/46 , H01M50/403 , H01M50/411
摘要： Provided herein is a lithium battery including: a cathode including a cathode active material; an anode including an anode active material; an electrolyte between the cathode and the anode; and a separator impregnated with the electrolyte, wherein the separator includes cellulose nanofibers, and wherein a differential scanning calorimetry (DSC) thermogram of the separator evinces an exothermic reaction peak, represented by a differential value (dH/dT), at a temperature in a range of about 150° C. to about 200° C.

36. 发明授权

US09196364B2 Nonvolatile memory device having split ground selection line structures 有权
标题翻译：具有分割地选择线结构的非易失性存储器件
公开(公告)号：US09196364B2
公开(公告)日：2015-11-24
申请号：US14244930
申请日：2014-04-04
申请人： Minsu Kim , Yang-Lo Ahn , Dae Han Kim , Kitae Park
发明人： Minsu Kim , Yang-Lo Ahn , Dae Han Kim , Kitae Park
IPC分类号： G11C16/04 , G11C16/08 , G11C16/34
CPC分类号： G11C16/08 , G11C16/0483 , G11C16/3427
摘要： A nonvolatile memory device includes a plurality of vertical NAND flash memory cells arranged in a three dimensional (3D) structure, a first memory block disposed in the 3D structure and having memory cells selected by a first ground selection line and a second ground selection line, wherein the first and second ground selection lines are electrically separated from each other, a second memory block disposed in the 3D structure and having memory cells selected by a third selection line and fourth selection line, wherein the third and fourth ground selection lines are electrically separated from each other, and a pass transistor that transfers a driving signal to turn on ground selection transistors respectively connected to the first and third ground selection lines in response to a block selection signal.
摘要翻译：非易失性存储器件包括以三维（3D）结构排列的多个垂直NAND闪存单元，设置在3D结构中并具有由第一地选择线和第二地选择线选择的存储单元的第一存储块，其中所述第一和第二接地选择线彼此电分离，设置在所述3D结构中并具有由第三选择线和第四选择线选择的存储单元的第二存储器块，其中所述第三和第四接地选择线被电分离以及传递驱动信号以通过响应于块选择信号接通分别连接到第一和第三接地选择线的接地选择晶体管的传输晶体管。

37. 发明申请

US20150153955A1 MEMORY SYSTEM AND USER DEVICE INCLUDING THE SAME 有权
标题翻译：存储器系统和包括其的用户设备
公开(公告)号：US20150153955A1
公开(公告)日：2015-06-04
申请号：US14466187
申请日：2014-08-22
申请人： Donghun KWAK , Kitae PARK
发明人： Donghun KWAK , Kitae PARK
IPC分类号： G06F3/06
CPC分类号： G11C16/349 , G06F12/0246 , G06F2003/0697 , G11C16/0466 , G11C16/26
摘要： In one embodiment, the method includes receiving a read request for reading data from a memory area of the memory, and determining whether an identifier of the memory area is stored in one of the plurality of entries of a characteristic table. Each of the plurality of entries is associated with a different range of at least one memory area characteristic and each of the plurality of entries is associated with different read condition information. The method further includes obtaining the read condition information associated with the entry storing the identifier of the memory area if the determining determines the identifier is stored in one of the plurality of entries of the characteristic table, and controlling the memory to read data from the memory area using the obtained read condition information.
摘要翻译：在一个实施例中，该方法包括从存储器的存储器区域接收读取数据的读取请求，以及确定存储器区域的标识符是否存储在特征表的多个条目之一中。多个条目中的每一个与至少一个存储器区域特征的不同范围相关联，并且多个条目中的每一个与不同的读取条件信息相关联。该方法还包括：如果确定确定标识符存储在特征表的多个条目之一，并且控制存储器从存储器读取数据，则获得与存储存储区域的标识符的条目相关联的读取条件信息区域，使用获得的读取条件信息。

38. 发明申请

US20150103597A1 NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF NONVOLATILE MEMORY SYSTEM 有权
标题翻译：非易失性存储器件，非易失性存储器系统，包括非易失性存储器件以及非易失性存储器系统的操作方法
公开(公告)号：US20150103597A1
公开(公告)日：2015-04-16
申请号：US14467920
申请日：2014-08-25
申请人： HYUN-WOOK PARK , KITAE PARK , JAEYONG JEONG
发明人： HYUN-WOOK PARK , KITAE PARK , JAEYONG JEONG
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/14 , G11C11/56 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3418 , G11C16/3445
摘要： An method of operating a memory system including a plurality of memory cells includes changing an operation mode at least some of the memory cells which operate based on a first operation mode to operate based on a second operation mode; and performing a change erase operation on the memory cells for which an operation mode is changed on the basis of a change erase condition when the operation mode is changed. When memory cells operate in the first operation mode, a normal erase operation is performed based on a first erase condition, and when memory cells operate in the second operation mode, a normal erase operation is performed based on a second erase condition. The change erase condition is different from at least one of the first and second erase conditions.
摘要翻译：一种操作包括多个存储器单元的存储器系统的方法包括：根据第二操作模式，改变基于第一操作模式操作的至少一些存储器单元的操作模式; 并且当操作模式改变时，基于改变擦除条件，对在其中改变操作模式的存储单元执行改变擦除操作。当存储单元在第一操作模式下工作时，基于第一擦除条件执行正常擦除操作，并且当存储器单元在第二操作模式下操作时，基于第二擦除条件执行正常擦除操作。改变擦除条件不同于第一和第二擦除条件中的至少一个。

39. 发明申请

US20150036426A1 NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAM VERIFYING THE SAME 有权
标题翻译：非易失性存储器件及其验证方法
公开(公告)号：US20150036426A1
公开(公告)日：2015-02-05
申请号：US14284031
申请日：2014-05-21
申请人： DONGHUN KWAK , HYUN-WOOK PARK , KITAE PARK
发明人： DONGHUN KWAK , HYUN-WOOK PARK , KITAE PARK
IPC分类号： G11C16/10 , G11C16/34 , G11C16/26
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/10 , G11C16/26
摘要： A program method of a three-dimensional nonvolatile memory device is provided which includes executing at least one program loop including an operation of programming selected memory cells of a selected string turned on by a selected string selection transistor and an operation of verifying whether programming of the memory cells is passed; and applying a negative counter voltage to a selected word line connected to the selected memory cells of the selected string at least once during an interval of the verify operation where there are turned on string selection transistors of unselected strings connected through the same bit line as that of the selected string.
摘要翻译：提供了一种三维非易失性存储器件的编程方法，包括执行至少一个程序循环，该程序循环包括对由所选择的字符串选择晶体管导通的所选字符串的选定存储单元进行编程的操作，以及验证是否对记忆细胞通过; 以及在验证操作的间隔期间至少一次将连接到所选字符串的所选择的存储单元的选定字线施加负的反电压，其中通过与该相同的位线连接的未选择的串连接的串选择晶体管，的选定字符串。

40. 发明申请

US20150003169A1 NONVOLATILE MEMORY DEVICE, A MEMORY SYSTEM HAVING THE SAME, AND A READ METHOD THEREOF 有权
标题翻译：非易失存储器件，具有该存储器件的存储器系统及其读取方法
公开(公告)号：US20150003169A1
公开(公告)日：2015-01-01
申请号：US14242332
申请日：2014-04-01
申请人： Sang-Wan Nam , Kitae Park , Hyun-Wook Park , Jae-Kyun Rhee
发明人： Sang-Wan Nam , Kitae Park , Hyun-Wook Park , Jae-Kyun Rhee
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/3427
摘要： A method of reading a nonvolatile memory device including: applying a read voltage to a selected wordline of the nonvolatile memory device; applying a read pass voltage to unselected wordlines of the nonvolatile memory device; sensing a state of a memory cell connected to the selected wordline; and applying the read pass voltage to the selected wordline after the sensing.
摘要翻译：一种读取非易失性存储器件的方法，包括：将读取电压施加到非易失性存储器件的选定字线; 对非易失性存储器件的未选字线施加读通过电压; 感测连接到所选字线的存储单元的状态; 并且在感测之后将读通道电压施加到所选择的字线。

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