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31. 发明授权

US07696051B2 Method of fabricating a MOSFET having doped epitaxially grown source/drain region on recessed substrate 失效
标题翻译：制造在凹陷衬底上具有掺杂的外延生长源/漏区的MOSFET的方法
公开(公告)号：US07696051B2
公开(公告)日：2010-04-13
申请号：US11177185
申请日：2005-07-07
申请人： You-seung Jin , Jong-hyon Ahn
发明人： You-seung Jin , Jong-hyon Ahn
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/6653 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A MOSFET includes a semiconductor substrate with a first region having a relatively thick first thickness and a second region having a relatively thin second thickness; a gate insulating layer pattern formed on the first region of the semiconductor substrate; a gate conductive layer pattern formed on the gate insulating layer pattern; an epitaxial layer formed on the second region of the semiconductor substrate so as to have a predetermined thickness; spacers formed on sidewalls of the gate conductive layer pattern and part of the surface of the epitaxial layer; a lightly-doped first impurity region formed in the semiconductor substrate disposed below the spacers and in the epitaxial layer; and a heavily-doped second impurity region formed in a portion of the semiconductor substrate, exposed by the spacers.
摘要翻译： MOSFET包括具有第一区域和第二区域的半导体衬底，第一区域具有相对较厚的第一厚度，第二区域具有相对较薄的第二厚度; 形成在所述半导体衬底的所述第一区域上的栅极绝缘层图案; 形成在所述栅极绝缘层图案上的栅极导电层图案; 外延层，形成在半导体衬底的第二区域上以具有预定厚度; 间隔物形成在栅极导电层图案的侧壁和外延层表面的一部分上; 形成在所述半导体衬底中的轻掺杂的第一杂质区域，所述半导体衬底设置在所述间隔物的下方和所述外延层中; 以及形成在半导体衬底的由间隔物暴露的部分中的重掺杂的第二杂质区。

32. 发明申请

US20090051014A1 Method of fabricating semiconductor device having silicide layer and semiconductor device fabricated thereby 审中-公开
标题翻译：制造具有硅化物层的半导体器件及其制造的半导体器件的方法
公开(公告)号：US20090051014A1
公开(公告)日：2009-02-26
申请号：US12285851
申请日：2008-10-15
申请人： Ki-seog Youn , Jong-hyon Ahn , Su-gon Bae
发明人： Ki-seog Youn , Jong-hyon Ahn , Su-gon Bae
IPC分类号： H01L29/06
CPC分类号： H01L21/823443 , H01L21/823418
摘要： A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.
摘要翻译：提供一种制造具有硅化物层的半导体器件的方法和通过该方法制造的半导体器件。该方法可以包括提供具有有源区和场区的半导体衬底，并且在有源区和场区中的每一个上形成多个栅极图案。多个栅极图案可以各自具有侧壁间隔物。场区域上的多个栅极图案包括至少两个相邻的栅极图案。该方法可以包括形成硅化物阻挡层图案，其掩蔽存在于场区域上的每个相邻栅极图案之间的场区域的一部分。该方法还可以包括在有源区上形成硅化物层以及未被硅化物阻挡层图案掩蔽的多个栅极图案中的任何一个。

33. 发明授权

US07358588B2 Trench isolation type semiconductor device which prevents a recess from being formed in a field region 有权
标题翻译：沟槽隔离型半导体器件防止在场区域中形成凹陷
公开(公告)号：US07358588B2
公开(公告)日：2008-04-15
申请号：US11301510
申请日：2005-12-13
申请人： Ki-seog Youn , Jong-hyon Ahn , Deok-hyung Lee , Sung-gun Kang , Kong-soo Cheong
发明人： Ki-seog Youn , Jong-hyon Ahn , Deok-hyung Lee , Sung-gun Kang , Kong-soo Cheong
IPC分类号： H01L29/00
CPC分类号： H01L21/76224
摘要： A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.
摘要翻译：提供其中防止在场区域中形成凹部的沟槽隔离型半导体器件及其制造方法。沟槽隔离型半导体器件包括由有源区和场区定义的半导体衬底，在场区中形成的沟槽，沿着沟内部保形地形成的氧化物层，沿着氧化物层保形地形成的衬层，形成在包括氧化物层和衬垫层的沟槽内的场绝缘层，以及形成在场绝缘层上的场保护层，使得半导体衬底上不发生阶差。

34. 发明申请

US20080026519A1 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080026519A1
公开(公告)日：2008-01-31
申请号：US11878351
申请日：2007-07-24
申请人： Jin Hua Liu , Jong-Hyon Ahn
发明人： Jin Hua Liu , Jong-Hyon Ahn
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/2822 , H01L29/42368 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： In a method of fabricating a semiconductor device, a first mask pattern is formed on a substrate. The first mask pattern has a first opening formed to expose the substrate. An oxidation barrier region is formed in the substrate exposed by the first opening, and the first mask pattern is patterned to form a second mask pattern having a second opening. A gate insulation layer is formed on the substrate exposed by the second opening. The gate insulation layer has a variable thickness.
摘要翻译：在制造半导体器件的方法中，在衬底上形成第一掩模图案。第一掩模图案具有形成为露出基板的第一开口。在由第一开口暴露的衬底中形成氧化阻挡区域，并且对第一掩模图案进行图案化以形成具有第二开口的第二掩模图案。在由第二开口暴露的基板上形成栅极绝缘层。栅极绝缘层具有可变的厚度。

35. 发明申请

US20070293045A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070293045A1
公开(公告)日：2007-12-20
申请号：US11808981
申请日：2007-06-14
申请人： Ki-Seog Youn , Jong-Hyon Ahn , Joo-Hyoung Lee , Kwang-Duk Kim
发明人： Ki-Seog Youn , Jong-Hyon Ahn , Joo-Hyoung Lee , Kwang-Duk Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/76224
摘要： A semiconductor device may include a semiconductor substrate having a trench, a device isolation layer filling the trench, and a liner nitride layer disposed between the semiconductor substrate and the device isolation layer. The device isolation layer may additionally cover a portion of the substrate surrounding the trench. The liner nitride layer may have an upper portion and a lower portion, wherein the upper portion may be thinner than the lower portion. The liner nitride layer may reduce or prevent a recess from being generated between an active region and a device isolation region. Accordingly, a relatively high-quality semiconductor device may be fabricated using a simplified process.
摘要翻译：半导体器件可以包括具有沟槽的半导体衬底，填充沟槽的器件隔离层以及设置在半导体衬底和器件隔离层之间的衬里氮化物层。器件隔离层可以另外覆盖围绕沟槽的衬底的一部分。衬里氮化物层可以具有上部和下部，其中上部可以比下部更薄。衬里氮化物层可以减少或防止在有源区和器件隔离区之间产生凹陷。因此，可以使用简化的工艺来制造相对高质量的半导体器件。

36. 发明申请

US20070257303A1 Transistor and method for forming the same 审中-公开
标题翻译：晶体管及其形成方法
公开(公告)号：US20070257303A1
公开(公告)日：2007-11-08
申请号：US11797429
申请日：2007-05-03
申请人： Jin Hua Liu , Jong-Hyon Ahn
发明人： Jin Hua Liu , Jong-Hyon Ahn
IPC分类号： H01L21/8238 , H01L29/788 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A deep source/drain region and a source/drain extension region may be formed in a semiconductor substrate adjacent to a gate electrode. A first silicide layer may be formed on the source/drain extension region. A gate spacer may be formed on a sidewall of the gate electrode to cover the first silicide layer. A second silicide layer may be formed on the deep source/drain region outside the gate spacer.
摘要翻译：深源极/漏极区域和源极/漏极延伸区域可以形成在与栅电极相邻的半导体衬底中。可以在源极/漏极延伸区域上形成第一硅化物层。栅极间隔物可以形成在栅电极的侧壁上以覆盖第一硅化物层。第二硅化物层可以形成在栅极间隔物外部的深源极/漏极区域上。

37. 发明授权

US07288848B2 Overlay mark for measuring and correcting alignment errors 有权
标题翻译：用于测量和校正对准误差的叠加标记
公开(公告)号：US07288848B2
公开(公告)日：2007-10-30
申请号：US10997441
申请日：2004-11-23
申请人： Dong-Hun Lee , Jong-Hyon Ahn , Do-Yul Yoo , Sung-Gun Kang
发明人： Dong-Hun Lee , Jong-Hyon Ahn , Do-Yul Yoo , Sung-Gun Kang
IPC分类号： H01L23/544
CPC分类号： G03F7/70633 , H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , H01L2924/00
摘要： An overlay mark includes at least one hole array formed on a semiconductor substrate and at least one linear trench adjacent to the hole array. The hole array may be formed adjacent to the linear trench along a predetermined direction. When alignment errors among patterns formed at predetermined portion of the semiconductor substrate are detected, the overlay mark may provide a contrast of light with a desired width and a high level so that alignment errors of patterns formed on the semiconductor substrate may be accurately detected and corrected using the overlay mark.
摘要翻译：覆盖标记包括形成在半导体衬底上的至少一个孔阵列和与孔阵列相邻的至少一个线性沟槽。孔阵列可以沿着预定方向形成为与线性沟槽相邻。当检测到在半导体衬底的预定部分形成的图形之间的对准误差时，重叠标记可以提供具有所需宽度和高电平的光的对比度，从而可以精确地检测和校正形成在半导体衬底上的图案的对准误差使用重叠标记。

38. 发明申请

US20060099766A1 Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance 失效
公开(公告)号：US20060099766A1
公开(公告)日：2006-05-11
申请号：US11313631
申请日：2005-12-21
申请人： You-Seung Jin , Jong-Hyon Ahn , Hyuk-Ju Ryu
发明人： You-Seung Jin , Jong-Hyon Ahn , Hyuk-Ju Ryu
IPC分类号： H01L21/336
CPC分类号： H01L29/4925 , H01L21/28035 , H01L21/28044 , H01L21/28052 , H01L21/28114 , H01L21/823425 , H01L21/823437 , H01L21/823443 , H01L21/823468 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/78 , H01L29/7833
摘要： In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion of the gate electrode is exposed. A silicon epitaxial layer is selectively formed only on the exposed gate electrode, and the planarized layer is completely removed. A gate spacer is formed along side surfaces of the gate electrode and the silicon epitaxial layer. A source/drain region is formed on a surface portion of the active region corresponding to the gate electrode. Since the silicon epitaxial layer is formed only on the gate region except the source/drain region, the gate resistance is stabilized and the parasitic capacitance between the gate electrode and the source/drain region is reduce.

39. 发明申请

US20050285161A1 Method of fabricating multi-gate transistor and multi-gate transistor fabricated thereby 审中-公开
标题翻译：制造由此制造多栅极晶体管和多栅极晶体管的方法
公开(公告)号：US20050285161A1
公开(公告)日：2005-12-29
申请号：US11103115
申请日：2005-04-11
申请人： Tae-woong Kang , Jong-hyon Ahn
发明人： Tae-woong Kang , Jong-hyon Ahn
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/786
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： Provided are a method of fabricating an improved multi-gate transistor and a multi-gate transistor fabricated using the method, which can reproduce a profile of a gate electrode in a stable manner. The method includes forming an active pattern on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed, forming a gate insulating layer on the channel regions, and forming a patterned gate electrode on the gate insulating layer while maintaining a shape conformal to the active pattern.
摘要翻译：提供了一种制造改进的多栅极晶体管和使用该方法制造的多栅极晶体管的方法，其可以以稳定的方式再现栅电极的轮廓。所述方法包括在衬底上形成有源图案，所述有源图案具有两个或多个要在其上形成沟道区的表面，在沟道区上形成栅极绝缘层，以及在栅极绝缘层上形成图案化栅电极，同时保持与活动图案一致的形状。

40. 发明授权

US06768199B2 Flip chip type semiconductor device and method of fabricating the same 失效
标题翻译：倒装芯片型半导体器件及其制造方法
公开(公告)号：US06768199B2
公开(公告)日：2004-07-27
申请号：US09974025
申请日：2001-10-10
申请人： Jung-Lim Yoon , Jong-Hyon Ahn , Chang-Hun Lee
发明人： Jung-Lim Yoon , Jong-Hyon Ahn , Chang-Hun Lee
IPC分类号： H01L2348
CPC分类号： H01L24/10 , H01L23/5258 , H01L23/528 , H01L24/13 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05181 , H01L2224/05572 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01078 , H01L2924/01082 , H01L2924/04953 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2224/05552 , H01L2924/00 , H01L2924/00014
摘要： A flip chip type semiconductor device comprises at least one first metal line and at least a pair of second metal lines formed in the passivation layer, an aluminum pad covering the first metal line, an aluminum fuse covering the pair of second metal lines adjacent to each other and the passivation layer therebetween, and an under-bump metal layer pattern and a bump formed on the aluminum pad in order. The first and second metal lines are formed respectively in first and second grooves by using a damascene process after forming first and second grooves in the passivation layer.
摘要翻译：倒装芯片型半导体器件包括至少一个第一金属线和形成在钝化层中的至少一对第二金属线，覆盖第一金属线的铝焊盘，覆盖与每个第二金属线相邻的一对第二金属线的铝保险丝其它和其间的钝化层，以及凸起下方的金属层图案和形成在铝焊盘上的凸块。在钝化层中形成第一和第二凹槽之后，通过使用镶嵌工艺分别在第一和第二凹槽中形成第一和第二金属线。

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