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31. 发明申请

US20060110900A1 Method of forming a gate of a semiconductor device 有权
标题翻译：形成半导体器件的栅极的方法
公开(公告)号：US20060110900A1
公开(公告)日：2006-05-25
申请号：US11283121
申请日：2005-11-18
申请人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Jang-Hee Lee , Jae-Hwa Park , Dong-Chan Lim , Byung-Hak Lee , Hee-Sook Park
发明人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Jang-Hee Lee , Jae-Hwa Park , Dong-Chan Lim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/28247 , H01L21/28044 , H01L29/4925
摘要： In a method for forming a gate in a semiconductor device, a first preliminary gate structure is formed on a substrate. The first preliminary gate structure includes a gate oxide layer, a polysilicon layer pattern and a tungsten layer pattern sequentially stacked on the substrate. A primary oxidation process is performed using oxygen radicals at a first temperature for adjusting a thickness of the gate oxide layer to form a second preliminary gate structure having tungsten oxide. The tungsten oxide is reduced to a tungsten material using a gas containing hydrogen to form a gate structure. The tungsten oxide may not be formed on the gate structure so that generation of the whiskers may be suppressed. Thus, a short between adjacent wirings may not be generated.
摘要翻译：在半导体器件中形成栅极的方法中，在衬底上形成第一预栅极结构。第一预选栅极结构包括依次层叠在基板上的栅极氧化物层，多晶硅层图案和钨层图案。在第一温度下使用氧自由基进行一次氧化处理，以调节栅极氧化物层的厚度以形成具有氧化钨的第二初步栅极结构。使用含氢气体将钨氧化物还原成钨材料以形成栅极结构。在栅极结构上可能不形成氧化钨，从而可以抑制晶须的产生。因此，可能不会产生相邻布线之间的短路。

32. 发明申请

US20060091436A1 Methods of forming field effect transistors having metal silicide gate electrodes 有权
标题翻译：形成具有金属硅化物栅电极的场效应晶体管的方法
公开(公告)号：US20060091436A1
公开(公告)日：2006-05-04
申请号：US11230586
申请日：2005-09-20
申请人： Hyun-Su Kim , Jong-Ho Yun , Byung-Hak Lee , Eun-Ji Jung , Gil-Heyun Choi
发明人： Hyun-Su Kim , Jong-Ho Yun , Byung-Hak Lee , Eun-Ji Jung , Gil-Heyun Choi
IPC分类号： H01L29/94
CPC分类号： H01L21/28097 , H01L21/823835 , H01L29/4975 , H01L29/665 , H01L29/66545
摘要： Methods of forming field effect transistors according to embodiments of the invention include forming a conductive gate electrode (e.g., polysilicon gate electrode) on a semiconductor substrate and forming a first metal layer on the conductive gate electrode. This first metal layer may include a material selected from a group consisting of nickel, cobalt, titanium, tantalum and tungsten. The first metal layer and the conductive gate electrode are thermally treated for a sufficient duration to convert a first portion of the conductive gate electrode into a first metal silicide region. The first metal layer and the first metal silicide region are then removed to expose a second portion of the conductive gate electrode. A second metal layer is then formed on the second portion of the conductive gate electrode. This second metal layer may include a material selected from a group consisting of nickel, cobalt, titanium, tantalum and tungsten. The second metal layer and the second portion of the conductive gate electrode are thermally treated for a sufficient duration to thereby convert the second portion of the conductive gate electrode into a second metal silicide region.
摘要翻译：根据本发明的实施例的形成场效应晶体管的方法包括在半导体衬底上形成导电栅电极（例如，多晶硅栅电极），并在导电栅电极上形成第一金属层。该第一金属层可以包括选自镍，钴，钛，钽和钨的材料。对第一金属层和导电栅电极进行热处理足够的时间以将导电栅电极的第一部分转换成第一金属硅化物区域。然后去除第一金属层和第一金属硅化物区域以暴露导电栅电极的第二部分。然后在导电栅电极的第二部分上形成第二金属层。该第二金属层可以包括选自镍，钴，钛，钽和钨的材料。第二金属层和导电栅电极的第二部分被热处理足够的持续时间，从而将导电栅电极的第二部分转换成第二金属硅化物区域。

33. 发明申请

US20060014355A1 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US20060014355A1
公开(公告)日：2006-01-19
申请号：US11233580
申请日：2005-09-23
申请人： Jae-Hwa Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Sohn , Jong-Ryeol Yoo , Sun-Pil Yun , Jang-Hee Lee , Dong-Chan Lim
发明人： Jae-Hwa Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Sohn , Jong-Ryeol Yoo , Sun-Pil Yun , Jang-Hee Lee , Dong-Chan Lim
IPC分类号： H01L21/20
CPC分类号： H01L21/76841 , H01L21/28061 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L29/4933 , H01L29/4941
摘要： Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming the semiconductor devices. A resistance reducing layer is formed between a polysilicon layer and a metal layer. As a result, an interface resistance between the polysilicon layer and the metal layer is greatly reduced and a distribution of the interface resistance is very uniform. As a result, a conductive structure including the resistance reducing layer has a greatly reduced sheet resistance to improve electrical characteristics of a semiconductor device having the conductive structure.

34. 发明授权

US06531820B1 Plasma display device including grooves concentrating an electric field 失效
标题翻译：等离子体显示装置，包括集中电场的槽
公开(公告)号：US06531820B1
公开(公告)日：2003-03-11
申请号：US09533787
申请日：2000-03-24
申请人： Byung-hak Lee , Eun-gi Heo , Min-sun Yoo , Yoshinori Anzai
发明人： Byung-hak Lee , Eun-gi Heo , Min-sun Yoo , Yoshinori Anzai
IPC分类号： H01J1749
CPC分类号： H01J11/12 , H01J11/38
摘要： A plasma display device includes a first substrate, an address electrode formed on an upper surface of the fist substrate, a first dielectric layer formed on the upper surface of the first substrate and embedding the address electrode, a second substrate which is transparent and forms a discharge space by being coupled to the first substrate, a plurality of maintaining electrodes formed on a lower surface of the second substrate to form a predetermined angle with the address electrode, each of the maintaining electrodes including first and second electrodes, a second dielectric layer formed on the second substrate where the maintaining electrodes are formed and embedding the maintaining electrodes, at least a portion where an electrical field is concentrated formed between the first and second electrodes constituting the maintaining electrodes, and a partition installed between the first and second substrates for sectioning the discharge space.
摘要翻译：等离子体显示装置包括第一基板，形成在第一基板的上表面上的寻址电极，形成在第一基板的上表面上并嵌入寻址电极的第一电介质层，透明的第二基板，放电空间通过耦合到第一衬底，形成在第二衬底的下表面上以与寻址电极形成预定角度的多个保持电极，每个保持电极包括第一和第二电极，形成第二电介质层在形成维持电极的第二基板上并埋设保持电极的情况下，在构成保持电极的第一和第二电极之间至少形成电场集中的部分，以及安装在第一和第二基板之间用于切割的隔板放电空间。

35. 发明授权

US06432801B1 Gate electrode in a semiconductor device and method for forming thereof 失效
标题翻译：半导体器件中的栅电极及其形成方法
公开(公告)号：US06432801B1
公开(公告)日：2002-08-13
申请号：US09556817
申请日：2000-04-21
申请人： Byung Hak Lee
发明人： Byung Hak Lee
IPC分类号： H01L213205
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/28247
摘要： The present invention relates to a method for forming a gate electrode in a semiconductor device, which can improve GOI characteristics and allows for an effective suppression of metal silicide spike formation. This method includes the steps of forming a gate insulating film over a semiconductor substrate, forming a first semiconductor layer over the gate insulating film, forming a barrier layer over the first semiconductor layer to prevent formation of metal silicide spikes in the first semiconductor layer, forming a second semiconductor layer over the barrier layer, and forming a metal silicide layer over the second semiconductor layer.
摘要翻译：本发明涉及一种在半导体器件中形成栅电极的方法，其可以改善GOI特性并允许有效抑制金属硅化物尖峰形成。该方法包括以下步骤：在半导体衬底上形成栅极绝缘膜，在栅极绝缘膜上形成第一半导体层，在第一半导体层上形成阻挡层，以防止在第一半导体层中形成金属硅化物尖峰，形成在所述阻挡层上方的第二半导体层，以及在所述第二半导体层上形成金属硅化物层。

36. 发明授权

US06335297B1 Method for forming conductive line of semiconductor device 有权
标题翻译：形成半导体器件导线的方法
公开(公告)号：US06335297B1
公开(公告)日：2002-01-01
申请号：US09592438
申请日：2000-06-12
申请人： Chang Hee Han , Byung Hak Lee
发明人： Chang Hee Han , Byung Hak Lee
IPC分类号： H01L2131
CPC分类号： H01L21/28061 , H01L21/2807 , H01L29/4925
摘要： Method for forming a conductive line of a semiconductor device which has a high thermal stability and low electrical resistance includes the steps of forming an insulating layer on a semiconductor substrate, sequentially forming a semiconductor layer and a tungsten film on the insulating layer, nitrifying the tungsten film with heat treatment, and selectively etching the tungsten film and the semiconductor layer.
摘要翻译：用于形成具有高热稳定性和低电阻的半导体器件的导线的方法包括以下步骤：在半导体衬底上形成绝缘层，在绝缘层上依次形成半导体层和钨膜，硝化钨膜，并且选择性地蚀刻钨膜和半导体层。

37. 发明授权

US6096630A Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US6096630A
公开(公告)日：2000-08-01
申请号：US949397
申请日：1997-10-14
申请人： Jeong Soo Byun , Byung Hak Lee
发明人： Jeong Soo Byun , Byung Hak Lee
IPC分类号： H01L21/20 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/10 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28061 , H01L21/823835
摘要： Method for fabricating a semiconductor device, is disclosed, which is suitable for improving a resistivity, including the steps of forming a silicon layer on a substrate, forming a crystalline metal silicide layer on the silicon layer, forming an amorphous metal silicide layer by injecting ions into the crystalline metal silicide layer, and crystallizing the amorphous metal silicide by heat treating the amorphous metal silicide.
摘要翻译：公开了用于制造半导体器件的方法，其适于提高电阻率，包括在衬底上形成硅层的步骤，在硅层上形成结晶金属硅化物层，通过注入离子形成非晶金属硅化物层进入结晶金属硅化物层，并通过热处理非晶金属硅化物使非晶金属硅化物结晶。

38. 发明授权

US08466052B2 Method of fabricating semiconductor device having buried wiring 有权
标题翻译：制造具有埋地布线的半导体器件的方法
公开(公告)号：US08466052B2
公开(公告)日：2013-06-18
申请号：US12704358
申请日：2010-02-11
申请人： Jong-min Baek , Hee-sook Park , Seong-hwee Cheong , Gil-heyun Choi , Byung-hak Lee , Tae-ho Cha , Jae-hwa Park , Su-kyoung Kim
发明人： Jong-min Baek , Hee-sook Park , Seong-hwee Cheong , Gil-heyun Choi , Byung-hak Lee , Tae-ho Cha , Jae-hwa Park , Su-kyoung Kim
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/321 , H01L21/3213
CPC分类号： H01L27/10891
摘要： A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method.
摘要翻译：制造半导体器件的方法可以包括在半导体衬底中形成沟槽，在沟槽的底表面和侧表面上形成第一导电层，并且在第一导电层上选择性地形成第二导电层以埋在沟。可以通过使用化学镀方法或使用金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）方法在第一导电层上选择性地形成第二导电层。

39. 发明授权

US07989892B2 Gate structure, and semiconductor device having a gate structure 有权
标题翻译：栅极结构和具有栅极结构的半导体器件
公开(公告)号：US07989892B2
公开(公告)日：2011-08-02
申请号：US12483761
申请日：2009-06-12
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L21/44
CPC分类号： H01L29/4933 , H01L21/28061 , H01L27/10873
摘要： A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer.
摘要翻译：栅极结构可以包括多晶硅层，多晶硅层上的金属层，金属层上的金属硅化物氮化物层和金属硅化物氮化物层上的氮化硅掩模。

40. 发明授权

US07781849B2 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07781849B2
公开(公告)日：2010-08-24
申请号：US12315436
申请日：2008-12-03
申请人： Jong-min Baek , Seong-hwee Cheong , Gil-heyun Choi , Tae-ho Cha , Hee-sook Park , Byung-hak Lee , Jae-hwa Park
发明人： Jong-min Baek , Seong-hwee Cheong , Gil-heyun Choi , Tae-ho Cha , Hee-sook Park , Byung-hak Lee , Jae-hwa Park
IPC分类号： H01L29/78 , H01L23/48 , H01L23/52 , H01L29/40 , H01L29/49
CPC分类号： H01L21/28061 , H01L29/4933
摘要： Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.
摘要翻译：提供半导体器件及其制造方法，更具体地说，具有低电阻的W-Ni合金薄层的半导体器件及其制造方法。半导体器件包括W-Ni合金薄层。 W-Ni合金薄层中的Ni的重量可以在W-Ni合金薄层的总重量的约0.01〜约5.0重量％的范围内。

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