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1. 发明申请

US20090315091A1 GATE STRUCTURE, AND SEMICONDUCTOR DEVICE HAVING A GATE STRUCTURE 有权
标题翻译：门结构和具有门结构的半导体器件
公开(公告)号：US20090315091A1
公开(公告)日：2009-12-24
申请号：US12483761
申请日：2009-06-12
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L29/49 , H01L27/10
CPC分类号： H01L29/4933 , H01L21/28061 , H01L27/10873
摘要： A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer
摘要翻译：栅极结构可以包括多晶硅层，多晶硅层上的金属层，金属层上的金属硅化物氮化物层和金属硅化物氮化物层上的氮化硅掩模

2. 发明授权

US07989892B2 Gate structure, and semiconductor device having a gate structure 有权
标题翻译：栅极结构和具有栅极结构的半导体器件
公开(公告)号：US07989892B2
公开(公告)日：2011-08-02
申请号：US12483761
申请日：2009-06-12
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L21/44
CPC分类号： H01L29/4933 , H01L21/28061 , H01L27/10873
摘要： A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer.
摘要翻译：栅极结构可以包括多晶硅层，多晶硅层上的金属层，金属层上的金属硅化物氮化物层和金属硅化物氮化物层上的氮化硅掩模。

3. 发明申请

US20110171818A1 METHODS OF FORMING A GATE STRUCTURE 有权
标题翻译：形成门结构的方法
公开(公告)号：US20110171818A1
公开(公告)日：2011-07-14
申请号：US13053923
申请日：2011-03-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A method of forming a gate structure can be provided by forming a tunnel insulation layer on a substrate and forming a floating gate on the tunnel insulation layer. A dielectric layer pattern can be on the floating gate and a control gate can be formed on the dielectric layer pattern, which can be provided by forming a first conductive layer pattern on the dielectric layer pattern. A metal ohmic layer pattern can be formed on the first conductive layer pattern. A diffusion preventing layer pattern can be formed on the metal ohmic layer pattern. An amorphous layer pattern can be formed on the diffusion preventing layer pattern forming a second conductive layer pattern on the amorphous layer pattern. The floating gate can be further formed by forming an additional first conductive layer pattern on the tunnel insulation layer. An additional metal ohmic layer pattern can be formed on the additional first conductive layer pattern. An additional diffusion preventing layer can be formed pattern on the additional metal ohmic layer pattern. An additional amorphous layer pattern can be formed on the additional diffusion preventing layer pattern and an additional second conductive layer pattern can be formed on the additional amorphous layer pattern.
摘要翻译：可以通过在衬底上形成隧道绝缘层并在隧道绝缘层上形成浮栅来提供形成栅极结构的方法。电介质层图案可以在浮动栅极上，并且可以在介电层图案上形成控制栅极，其可以通过在电介质层图案上形成第一导电层图案来提供。可以在第一导电层图案上形成金属欧姆层图案。可以在金属欧姆层图案上形成扩散防止层图案。可以在形成非晶层图案上的第二导电层图案的扩散防止层图案上形成非晶层图案。可以通过在隧道绝缘层上形成附加的第一导电层图案来进一步形成浮栅。另外的金属欧姆层图案可以形成在附加的第一导电层图案上。附加的扩散防止层可以在附加金属欧姆层图案上形成图案。可以在附加的防扩散层图案上形成附加的非晶层图案，并且可以在附加的非晶层图案上形成附加的第二导电层图案。

4. 发明授权

US07928498B2 Gate structures in semiconductor devices 有权
标题翻译：半导体器件中的栅极结构
公开(公告)号：US07928498B2
公开(公告)日：2011-04-19
申请号：US12428303
申请日：2009-04-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.
摘要翻译：栅极结构包括在衬底上的绝缘层，绝缘层上的第一导电层图案，第一导电层图案上的金属欧姆层图案，金属欧姆层图案上的扩散防止层图案，扩散防止层图案和非晶层图案上的第二导电层图案。栅极结构可以具有低的薄层电阻和期望的热稳定性。

5. 发明授权

US08404576B2 Methods of forming a gate structure 有权
标题翻译：形成栅极结构的方法
公开(公告)号：US08404576B2
公开(公告)日：2013-03-26
申请号：US13053923
申请日：2011-03-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L21/283
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion reduction layer pattern on the metal ohmic layer pattern an amorphous layer pattern on the diffusion reduction layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.
摘要翻译：栅极结构包括在衬底上的绝缘层，绝缘层上的第一导电层图案，第一导电层图案上的金属欧姆层图案，金属欧姆层图案上的扩散减少层图案，其上的非晶层图案扩散减少层图案和非晶层图案上的第二导电层图案。栅极结构可以具有低的薄层电阻和期望的热稳定性。

6. 发明申请

US20090267132A1 GATE STRUCTURES IN SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件的栅结构
公开(公告)号：US20090267132A1
公开(公告)日：2009-10-29
申请号：US12428303
申请日：2009-04-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L29/788 , H01L29/78 , H01L29/792
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.
摘要翻译：栅极结构包括在衬底上的绝缘层，绝缘层上的第一导电层图案，第一导电层图案上的金属欧姆层图案，金属欧姆层图案上的扩散防止层图案，扩散防止层图案和非晶层图案上的第二导电层图案。栅极结构可以具有低的薄层电阻和期望的热稳定性。

7. 发明授权

US07879737B2 Methods for fabricating improved gate dielectrics 有权
标题翻译：制造改进的栅极电介质的方法
公开(公告)号：US07879737B2
公开(公告)日：2011-02-01
申请号：US12801115
申请日：2010-05-24
申请人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
发明人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
IPC分类号： H01L21/31
CPC分类号： H01L21/823481 , H01L21/28202 , H01L21/28211 , H01L21/2822 , H01L29/518 , H01L29/66545 , H01L29/78 , Y10S438/981
摘要： Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.
摘要翻译：公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。这些方法提供了常规GPOX工艺的替代方案，并提供改进的耐漏电性，而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。每种方法包括形成第一开口以暴露有源区域区域，在暴露部分上形成氧化控制区域，然后形成第二开口，由此暴露氧化控制区域的外围区域以形成栅极介电层。得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

8. 发明授权

US07759263B2 Methods for fabricating improved gate dielectrics 失效
标题翻译：制造改进的栅极电介质的方法
公开(公告)号：US07759263B2
公开(公告)日：2010-07-20
申请号：US11806338
申请日：2007-05-31
申请人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
发明人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
IPC分类号： H01L21/336
CPC分类号： H01L21/823481 , H01L21/28202 , H01L21/28211 , H01L21/2822 , H01L29/518 , H01L29/66545 , H01L29/78 , Y10S438/981
摘要： Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.
摘要翻译：公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。这些方法提供了常规GPOX工艺的替代方案，并提供改进的耐漏电性，而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。每种方法包括形成第一开口以暴露有源区域区域，在暴露部分上形成氧化控制区域，然后形成第二开口，由此暴露氧化控制区域的外围区域以形成栅极介电层。得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

9. 发明申请

US20080014700A1 Methods for fabricating improved gate dielectrics 失效
标题翻译：制造改进的栅极电介质的方法
公开(公告)号：US20080014700A1
公开(公告)日：2008-01-17
申请号：US11806338
申请日：2007-05-31
申请人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
发明人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
IPC分类号： H01L21/336
CPC分类号： H01L21/823481 , H01L21/28202 , H01L21/28211 , H01L21/2822 , H01L29/518 , H01L29/66545 , H01L29/78 , Y10S438/981
摘要： Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.
摘要翻译：公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。这些方法提供了常规GPOX工艺的替代方案，并提供改进的耐漏电性，而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。每种方法包括形成第一开口以暴露有源区域区域，在暴露部分上形成氧化控制区域，然后形成第二开口，由此暴露氧化控制区域的外围区域以形成栅极介电层。得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

10. 发明授权

US07550353B2 Method of forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US07550353B2
公开(公告)日：2009-06-23
申请号：US11685644
申请日：2007-03-13
申请人： Byung-Hak Lee , Woong-Hee Sohn , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park
发明人： Byung-Hak Lee , Woong-Hee Sohn , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park
IPC分类号： H01L21/8236
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11568
摘要： One embodiment of a method for forming a semiconductor device can include forming a gate pattern on a semiconductor substrate and performing a selective re-oxidation process on the gate pattern in gas ambient including hydrogen, oxygen, and nitrogen. When the gate pattern includes a tunnel insulation layer, a metal nitride layer and a metal layer, the selective re-oxidation process heals the etching damage of a gate pattern and simultaneously prevents oxidation of the metal nitride layer and a tungsten electrode.
摘要翻译：用于形成半导体器件的方法的一个实施例可以包括在半导体衬底上形成栅极图案，并且在包括氢，氧和氮在内的气体环境中对栅极图案进行选择性再氧化处理。当栅极图案包括隧道绝缘层，金属氮化物层和金属层时，选择性再氧化工艺会修复栅极图案的蚀刻损伤，同时防止金属氮化物层和钨电极的氧化。

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