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1. 发明申请

US20110306205A1 Semiconductor Device and Method of Fabricating the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110306205A1
公开(公告)日：2011-12-15
申请号：US13105195
申请日：2011-05-11
申请人： Byung-Hak Lee , Yu-Gyun Shin , Sang-Woo Lee , Sun-Ghil Lee , Jin-Bum Kim , Joon-Gon Lee
发明人： Byung-Hak Lee , Yu-Gyun Shin , Sang-Woo Lee , Sun-Ghil Lee , Jin-Bum Kim , Joon-Gon Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518 , H01L21/823807 , H01L21/823814
摘要： Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time. The sequentially performed first and second heat-treatment processes convert the Ni metal layer on the source and drain regions into a NiSi layer on the source and drain regions and a NiSi2 layer between the NiSi layer and the source and drain regions.
摘要翻译：形成半导体器件的方法包括提供具有包括晶体管的源极和漏极区域的区域的衬底。在包括源极和漏极区域的衬底区域上形成镍（Ni）金属膜。执行第一热处理工艺，包括以第一斜率从第一温度至第二温度加热包括金属膜的基板，并将包含金属膜的基板在第二温度下保持第一时间段。然后执行第二热处理工艺，包括以第二斜率从第三温度至第四温度加热包括金属膜的衬底，并将衬底保持在第四温度第二时间段。第四温度与第二温度不同，第二时间段与第一时间段不同。依次执行的第一和第二热处理工艺将源极和漏极区域上的Ni金属层转换成源极和漏极区域上的NiSi层以及NiSi层与源极和漏极区域之间的NiSi 2层。

2. 发明授权

US07759263B2 Methods for fabricating improved gate dielectrics 失效
标题翻译：制造改进的栅极电介质的方法
公开(公告)号：US07759263B2
公开(公告)日：2010-07-20
申请号：US11806338
申请日：2007-05-31
申请人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
发明人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
IPC分类号： H01L21/336
CPC分类号： H01L21/823481 , H01L21/28202 , H01L21/28211 , H01L21/2822 , H01L29/518 , H01L29/66545 , H01L29/78 , Y10S438/981
摘要： Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.
摘要翻译：公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。这些方法提供了常规GPOX工艺的替代方案，并提供改进的耐漏电性，而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。每种方法包括形成第一开口以暴露有源区域区域，在暴露部分上形成氧化控制区域，然后形成第二开口，由此暴露氧化控制区域的外围区域以形成栅极介电层。得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

3. 发明授权

US07696552B2 Semiconductor devices including high-k dielectric materials 失效
标题翻译：包括高k电介质材料的半导体器件
公开(公告)号：US07696552B2
公开(公告)日：2010-04-13
申请号：US11227541
申请日：2005-09-15
申请人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Dong-Chan Lim , Jae-Hwa Park , Byung-Hak Lee , Hee-Sook Park
发明人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Dong-Chan Lim , Jae-Hwa Park , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/11526 , H01L21/82345 , H01L27/105 , H01L27/1052 , H01L27/11546
摘要： A semiconductor device includes a first conductive layer on a semiconductor substrate, a dielectric layer including a high-k dielectric material on the first conductive layer, a second conductive layer including polysilicon doped with P-type impurities on the dielectric layer, and a third conductive layer including a metal on the second conductive layer. In some devices, a first gate structure is formed in a main cell region and includes a tunnel oxide layer, a floating gate, a first high-k dielectric layer, and a control gate. The control gate includes a layer of polysilicon doped with P-type impurities and a metal layer. A second gate structure is formed outside the main cell region and includes a tunnel oxide layer, a conductive layer, and a metal layer. A third gate structure is formed in a peripheral cell region and includes a tunnel oxide, a conductive layer, and a high-k dielectric layer having a width narrower than the conductive layer. Method embodiments are also disclosed.
摘要翻译：半导体器件包括在半导体衬底上的第一导电层，在第一导电层上包括高k电介质材料的电介质层，在电介质层上掺杂有P型杂质的多晶硅的第二导电层，以及第三导电层层，其包括在第二导电层上的金属。在一些器件中，第一栅极结构形成在主单元区域中，并且包括隧道氧化物层，浮置栅极，第一高k电介质层和控制栅极。控制栅极包括掺杂有P型杂质和金属层的多晶硅层。第二栅极结构形成在主单元区域的外部，并且包括隧道氧化物层，导电层和金属层。第三栅极结构形成在周边单元区域中，并且包括具有比导电层窄的宽度的隧道氧化物，导电层和高k电介质层。还公开了方法实施例。

4. 发明授权

US07521316B2 Methods of forming gate structures for semiconductor devices 有权
标题翻译：形成半导体器件栅极结构的方法
公开(公告)号：US07521316B2
公开(公告)日：2009-04-21
申请号：US11221062
申请日：2005-09-07
申请人： Woong-Hee Sohn , Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Jong-Ryeol Yoo , Hee-Sook Park
发明人： Woong-Hee Sohn , Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Jong-Ryeol Yoo , Hee-Sook Park
IPC分类号： H01L21/00
CPC分类号： H01L21/28273 , H01L29/42324
摘要： Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.
摘要翻译：形成半导体器件的方法可以包括在半导体衬底上形成隧道氧化物层，在隧道氧化物层上形成栅极结构，形成漏电阻氧化物，形成绝缘衬垫。更具体地，隧道氧化物层可以在栅极结构和衬底之间，并且栅极结构可以包括隧道氧化物层上的第一栅极电极，第一栅电极上的栅极间电介质和第二栅电极所述栅极间电介质与所述第一和第二栅电极之间的栅极间电介质。漏电阻氧化物可以形成在第二栅电极的侧壁上。绝缘间隔物可以在绝缘隔离物和第二栅电极的侧壁之间的泄漏阻挡氧化物形成在漏电阻氧化物上。此外，绝缘间隔物和漏电阻氧化物可以包括不同的材料。还讨论了相关结构。

5. 发明申请

US20080014700A1 Methods for fabricating improved gate dielectrics 失效
标题翻译：制造改进的栅极电介质的方法
公开(公告)号：US20080014700A1
公开(公告)日：2008-01-17
申请号：US11806338
申请日：2007-05-31
申请人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
发明人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
IPC分类号： H01L21/336
CPC分类号： H01L21/823481 , H01L21/28202 , H01L21/28211 , H01L21/2822 , H01L29/518 , H01L29/66545 , H01L29/78 , Y10S438/981
摘要： Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.
摘要翻译：公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。这些方法提供了常规GPOX工艺的替代方案，并提供改进的耐漏电性，而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。每种方法包括形成第一开口以暴露有源区域区域，在暴露部分上形成氧化控制区域，然后形成第二开口，由此暴露氧化控制区域的外围区域以形成栅极介电层。得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

6. 发明授权

US07244511B2 Color steel sheet with embossed patterns on one side thereof 有权
标题翻译：彩色钢板，其一面具有压花图案
公开(公告)号：US07244511B2
公开(公告)日：2007-07-17
申请号：US11325828
申请日：2006-01-04
申请人： Jang Hyun Choi , Sung Su Jun , Sang Hoon Park , Won Young Lee , Byung Hak Lee
发明人： Jang Hyun Choi , Sung Su Jun , Sang Hoon Park , Won Young Lee , Byung Hak Lee
IPC分类号： B33B15/04 , B33B15/08 , B33B15/09 , B33B15/18
CPC分类号： C09D175/06 , B05D3/12 , B05D5/061 , B05D7/14 , B05D7/57 , B05D2202/15 , B05D2252/00 , B05D2350/65 , B05D2503/00 , C08G18/42 , C08G18/58 , Y10T428/12396 , Y10T428/12556 , Y10T428/12569 , Y10T428/12799 , Y10T428/12972 , Y10T428/26 , Y10T428/31681
摘要： A single-side embossed color steel sheet, and a method for manufacturing the same are disclosed. The steel sheet comprises a steel sheet substrate, a zinc or zinc alloy-plated layer, a non-chromate or chromate pretreated layer, a primary coat paint layer of modified epoxy or modified polyester, a color base paint layer, a printed layer, and a top coat clear paint layer. The printed layer exhibits a feeling of solidity with various feelings of texture and colors. The top coat clear paint layer serves to protect the printed layer from contaminants. The color steel sheet exhibits a remarkably enhanced feeling of solidity at an irregular surface thereof, and has enhanced contaminant resistance properties and environmental friendliness, thereby satisfying requirements for aesthetic design and functionality of products.
摘要翻译：公开了一种单面压纹彩色钢板及其制造方法。钢板包括钢板基材，锌或锌合金镀层，非铬酸盐或铬酸盐预处理层，改性环氧树脂或改性聚酯的初级涂层漆层，色底漆层，印刷层和顶漆清漆层。印刷层呈现出各种感觉的纹理和颜色的坚实感。顶层透明漆层用于保护印刷层免受污染。彩色钢板在其不规则表面显示出显着增强的坚固感，并且具有增强的耐污染性和环境友好性，从而满足了美学设计和产品功能的要求。

7. 发明申请

US20060115967A1 Methods of manufacturing a semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20060115967A1
公开(公告)日：2006-06-01
申请号：US11246791
申请日：2005-10-07
申请人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Jong-Ryeol Yoo , Dong-Chan Lim , Jae-Hwa Park , Sun-Pil Youn , Woong-Hee Sohn
发明人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Jong-Ryeol Yoo , Dong-Chan Lim , Jae-Hwa Park , Sun-Pil Youn , Woong-Hee Sohn
IPC分类号： H01L21/8238 , H01L21/425
CPC分类号： H01L21/823828
摘要： In a method of manufacturing a semiconductor device including a polysilicon layer on which a heat treatment is performed in hydrogen atmosphere, a preliminary polysilicon layer is formed on a semiconductor substrate. Fluorine (F) impurities are implanted onto the preliminary polysilicon layer, so that the preliminary polysilicon layer is formed into a polysilicon layer. A main heat treatment is performed on the polysilicon layer, thereby preventing a void caused by the fluorine (F) in the polysilicon layer. A subsidiary heat treatment is further performed on the polysilicon layer prior to the main heat treatment, thereby activating dopants in the polysilicon layer. Electrical characteristics and performance of a semiconductor device are improved since the void is sufficiently prevented in the polysilicon layer.
摘要翻译：在制造包括在氢气氛中进行热处理的多晶硅层的半导体器件的方法中，在半导体衬底上形成初步多晶硅层。将氟（F）杂质注入到初步多晶硅层上，使得初步多晶硅层形成为多晶硅层。在多晶硅层上进行主要的热处理，从而防止由多晶硅层中的氟（F）引起的空隙。在主要热处理之前在多晶硅层上进一步进行辅助热处理，由此激活多晶硅层中的掺杂剂。改善了半导体器件的电特性和性能，因为在多晶硅层中充分防止了空隙。

8. 发明申请

US20060079075A1 Gate structures with silicide sidewall barriers and methods of manufacturing the same 审中-公开
标题翻译：具有硅化物侧壁障碍的门结构及其制造方法
公开(公告)号：US20060079075A1
公开(公告)日：2006-04-13
申请号：US11201736
申请日：2005-08-11
申请人： Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Hee-Sook Park , Dong-Chan Lim , Jong-Ryeol Yoo , Woong-Hee Sohn
发明人： Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Hee-Sook Park , Dong-Chan Lim , Jong-Ryeol Yoo , Woong-Hee Sohn
IPC分类号： H01L21/3205
CPC分类号： H01L21/28061 , H01L29/4958 , H01L29/517
摘要： A gate structure includes a gate insulation layer on a substrate, a polysilicon layer pattern on the gate insulation layer, a composite metal layer pattern on the polysilicon layer pattern, and a metal silicide layer pattern on a sidewall of the composite metal layer pattern.
摘要翻译：栅极结构包括在衬底上的栅极绝缘层，栅极绝缘层上的多晶硅层图案，多晶硅层图案上的复合金属层图案以及复合金属层图案的侧壁上的金属硅化物层图案。

9. 发明申请

US20050266665A1 Methods of manufacturing semiconductor devices with gate structures having an oxide layer on the sidewalls thereof and related processing apparatus 审中-公开
标题翻译：制造具有在其侧壁上具有氧化物层的栅极结构的半导体器件的方法和相关的处理装置
公开(公告)号：US20050266665A1
公开(公告)日：2005-12-01
申请号：US11141401
申请日：2005-05-31
申请人： Sun-Pil Youn , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Shon , Jong-Ryeol Yoo
发明人： Sun-Pil Youn , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Shon , Jong-Ryeol Yoo
IPC分类号： H01L21/336 , H01L21/28 , H01L21/3205 , H01L21/321
CPC分类号： H01L21/28247 , H01L21/28061 , H01L21/32105
摘要： In a method of manufacturing a semiconductor device, a gate structure having a conductive layer pattern is formed on a substrate. The gate structure is then annealed. Oxygen radicals are applied to the gate structure to form an oxide layer on a sidewall of the conductive layer pattern.
摘要翻译：在制造半导体器件的方法中，在衬底上形成具有导电层图案的栅极结构。然后将栅极结构退火。将氧自由基施加到栅极结构以在导电层图案的侧壁上形成氧化物层。

10. 发明授权

US06531394B1 Method for forming gate electrode of semiconductor device 有权
标题翻译：形成半导体器件栅电极的方法
公开(公告)号：US06531394B1
公开(公告)日：2003-03-11
申请号：US09722820
申请日：2000-11-28
申请人： Byung Hak Lee
发明人： Byung Hak Lee
IPC分类号： H01L2144
CPC分类号： H01L21/28061 , H01L21/265 , H01L21/321 , H01L29/4941
摘要： A method for forming a gate electrode of a semiconductor device, which improves thermal stability of a tungsten/polysilicon structure. The method for forming a gate electrode of a semiconductor device includes: sequentially forming a first insulating film, a polysilicon layer and a tungsten layer on a semiconductor substrate; adding oxygen to the tungsten layer; forming a second insulating film on the tungsten layer to which oxygen is added; and selectively removing the second insulating film, the tungsten layer, the polysilicon layer and the first insulating film to form a gate electrode.
摘要翻译：一种形成半导体器件的栅电极的方法，其改善了钨/多晶硅结构的热稳定性。形成半导体器件的栅电极的方法包括：在半导体衬底上依次形成第一绝缘膜，多晶硅层和钨层; 向钨层中加入氧气; 在添加有氧的钨层上形成第二绝缘膜; 并且选择性地去除第二绝缘膜，钨层，多晶硅层和第一绝缘膜以形成栅电极。

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