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1. 发明授权

US08466052B2 Method of fabricating semiconductor device having buried wiring 有权
标题翻译：制造具有埋地布线的半导体器件的方法
公开(公告)号：US08466052B2
公开(公告)日：2013-06-18
申请号：US12704358
申请日：2010-02-11
申请人： Jong-min Baek , Hee-sook Park , Seong-hwee Cheong , Gil-heyun Choi , Byung-hak Lee , Tae-ho Cha , Jae-hwa Park , Su-kyoung Kim
发明人： Jong-min Baek , Hee-sook Park , Seong-hwee Cheong , Gil-heyun Choi , Byung-hak Lee , Tae-ho Cha , Jae-hwa Park , Su-kyoung Kim
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/321 , H01L21/3213
CPC分类号： H01L27/10891
摘要： A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method.
摘要翻译：制造半导体器件的方法可以包括在半导体衬底中形成沟槽，在沟槽的底表面和侧表面上形成第一导电层，并且在第一导电层上选择性地形成第二导电层以埋在沟。可以通过使用化学镀方法或使用金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）方法在第一导电层上选择性地形成第二导电层。

2. 发明申请

US20100210105A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING BURIED WIRING 有权
标题翻译：制造具有接线的半导体器件的方法
公开(公告)号：US20100210105A1
公开(公告)日：2010-08-19
申请号：US12704358
申请日：2010-02-11
申请人： Jong-min Baek , Hee-sook Park , Seong-hwee Cheong , Gil-heyun Choi , Byung-hak Lee , Tae-ho Cha , Jae-hwa Park , Su-kyoung Kim
发明人： Jong-min Baek , Hee-sook Park , Seong-hwee Cheong , Gil-heyun Choi , Byung-hak Lee , Tae-ho Cha , Jae-hwa Park , Su-kyoung Kim
IPC分类号： H01L21/768
CPC分类号： H01L27/10891
摘要： A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method.
摘要翻译：制造半导体器件的方法可以包括在半导体衬底中形成沟槽，在沟槽的底表面和侧表面上形成第一导电层，并且在第一导电层上选择性地形成第二导电层以埋在沟。可以通过使用化学镀方法或使用金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）方法在第一导电层上选择性地形成第二导电层。

3. 发明申请

US20090189229A1 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090189229A1
公开(公告)日：2009-07-30
申请号：US12315436
申请日：2008-12-03
申请人： Jong-min Baek , Seong-hwee Cheong , Gil-heyun Choi , Tae-ho Cha , Hee-sook Park , Byung-hak Lee , Jae-hwa Park
发明人： Jong-min Baek , Seong-hwee Cheong , Gil-heyun Choi , Tae-ho Cha , Hee-sook Park , Byung-hak Lee , Jae-hwa Park
IPC分类号： H01L21/283 , H01L23/532 , H01L29/78
CPC分类号： H01L21/28061 , H01L29/4933
摘要： Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.
摘要翻译：提供半导体器件及其制造方法，更具体地说，具有低电阻的W-Ni合金薄层的半导体器件及其制造方法。半导体器件包括W-Ni合金薄层。 W-Ni合金薄层中的Ni的重量可以在W-Ni合金薄层的总重量的约0.01〜约5.0重量％的范围内。

4. 发明授权

US07781849B2 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07781849B2
公开(公告)日：2010-08-24
申请号：US12315436
申请日：2008-12-03
申请人： Jong-min Baek , Seong-hwee Cheong , Gil-heyun Choi , Tae-ho Cha , Hee-sook Park , Byung-hak Lee , Jae-hwa Park
发明人： Jong-min Baek , Seong-hwee Cheong , Gil-heyun Choi , Tae-ho Cha , Hee-sook Park , Byung-hak Lee , Jae-hwa Park
IPC分类号： H01L29/78 , H01L23/48 , H01L23/52 , H01L29/40 , H01L29/49
CPC分类号： H01L21/28061 , H01L29/4933
摘要： Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.
摘要翻译：提供半导体器件及其制造方法，更具体地说，具有低电阻的W-Ni合金薄层的半导体器件及其制造方法。半导体器件包括W-Ni合金薄层。 W-Ni合金薄层中的Ni的重量可以在W-Ni合金薄层的总重量的约0.01〜约5.0重量％的范围内。

5. 发明申请

US20090101984A1 Semiconductor device having gate electrode including metal layer and method of manufacturing the same 审中-公开
标题翻译：具有包括金属层的栅电极的半导体器件及其制造方法
公开(公告)号：US20090101984A1
公开(公告)日：2009-04-23
申请号：US12003144
申请日：2007-12-20
申请人： Byung-hak Lee , Woong-hee Sohn , Jae-hwa Park , Gil-heyun Choi , Byung-hee Kim , Hee-sook Park
发明人： Byung-hak Lee , Woong-hee Sohn , Jae-hwa Park , Gil-heyun Choi , Byung-hee Kim , Hee-sook Park
IPC分类号： H01L29/78 , H01L27/092
CPC分类号： H01L21/823842 , H01L21/28052 , H01L21/28247
摘要： A semiconductor device may include a gate dielectric film on a semiconductor substrate and/or a gate electrode. The gate electrode may include a first metal film, a first metal silicide film, and/or a conductive polysilicon film sequentially stacked on the gate dielectric film.
摘要翻译：半导体器件可以包括在半导体衬底和/或栅电极上的栅极电介质膜。栅电极可以包括依次层叠在栅极电介质膜上的第一金属膜，第一金属硅化物膜和/或导电多晶硅膜。

6. 发明申请

US20080070405A1 Methods of forming metal wiring layers for semiconductor devices 审中-公开
标题翻译：形成半导体器件的金属布线层的方法
公开(公告)号：US20080070405A1
公开(公告)日：2008-03-20
申请号：US11800996
申请日：2007-05-08
申请人： Jae-hwa Park , Gil-heyun Choi , Jong-myeong Lee , Hee-sook Park
发明人： Jae-hwa Park , Gil-heyun Choi , Jong-myeong Lee , Hee-sook Park
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76856
摘要： A method of forming a conductive plug for an integrated circuit device may include forming an insulating layer on an integrated circuit substrate with the insulating layer having a surface opposite the substrate and a recess therein. A titanium (Ti) layer may be formed on sidewalls of the recess and on the surface of the insulating layer opposite the substrate. After forming the titanium (Ti) layer, a reaction reducing layer may be formed on portions of the titanium layer on the surface of the insulating layer opposite the substrate by at least one of ionized physical vapour deposition (iPVD) and/or nitriding a portion of the titanium layer, and the reaction reducing layer may include a material other than titanium. After forming the reaction reducing layer, a TiN layer may be formed on the reaction reducing layer and on sidewalls of the recess in the insulating layer using metal organic chemical vapour deposition (MOCVD). After forming the TiN layer, a conductive plug may be formed on the TiN layer in the recess in the insulating layer.
摘要翻译：形成用于集成电路器件的导电插塞的方法可以包括在集成电路衬底上形成绝缘层，绝缘层具有与衬底相对的表面和凹槽。钛（Ti）层可以形成在凹槽的侧壁上，并且在绝缘层的与衬底相对的表面上。在形成钛（Ti）层之后，可以通过离子物理气相沉积（iPVD）和/或氮化一部分中的至少一种，在绝缘层的与基板相对的表面上的钛层的部分上形成反应还原层的钛层，反应还原层可以包括钛以外的材料。在形成反应还原层之后，可以使用金属有机化学气相沉积（MOCVD）在反应还原层上和在绝缘层的凹槽的侧壁上形成TiN层。在形成TiN层之后，可以在绝缘层的凹部中的TiN层上形成导电塞。

7. 发明申请

US20050158990A1 Methods of forming metal wiring layers for semiconductor devices 审中-公开
标题翻译：形成半导体器件的金属布线层的方法
公开(公告)号：US20050158990A1
公开(公告)日：2005-07-21
申请号：US11033781
申请日：2005-01-12
申请人： Jae-hwa Park , Gil-heyun Choi , Jong-myeong Lee , Hee-sook Park
发明人： Jae-hwa Park , Gil-heyun Choi , Jong-myeong Lee , Hee-sook Park
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L29/15
CPC分类号： H01L21/7684 , H01L21/28556 , H01L21/76846 , H01L21/76856
摘要： A method of forming a conductive plug for an integrated circuit device may include forming an insulating layer on an integrated circuit substrate with the insulating layer having a surface opposite the substrate and a recess therein. A titanium (Ti) layer may be formed on sidewalls of the recess and on the surface of the insulating layer opposite the substrate. After forming the titanium (Ti) layer, a reaction reducing layer may be formed on portions of the titanium layer on the surface of the insulating layer opposite the substrate by at least one of ionized physical vapour deposition (iPVD) and/or nitriding a portion of the titanium layer, and the reaction reducing layer may include a material other than titanium. After forming the reaction reducing layer, a TiN layer may be formed on the reaction reducing layer and on sidewalls of the recess in the insulating layer using metal organic chemical vapour deposition (MOCVD). After forming the TiN layer, a conductive plug may be formed on the TiN layer in the recess in the insulating layer.
摘要翻译：形成用于集成电路器件的导电插塞的方法可以包括在集成电路衬底上形成绝缘层，绝缘层具有与衬底相对的表面和凹部。钛（Ti）层可以形成在凹槽的侧壁上，并且在绝缘层的与衬底相对的表面上。在形成钛（Ti）层之后，可以通过离子物理气相沉积（iPVD）和/或氮化一部分中的至少一种，在绝缘层的与基板相对的表面上的钛层的部分上形成反应还原层的钛层，反应还原层可以包括钛以外的材料。在形成反应还原层之后，可以使用金属有机化学气相沉积（MOCVD）在反应还原层上和在绝缘层的凹槽的侧壁上形成TiN层。在形成TiN层之后，可以在绝缘层的凹部中的TiN层上形成导电塞。

8. 发明申请

US20070197015A1 Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer 审中-公开
公开(公告)号：US20070197015A1
公开(公告)日：2007-08-23
申请号：US11787468
申请日：2007-04-17
申请人： Hee-sook Park , Gil-heyun Choi , Sang-bum Kang , Seong-geon Park , Kwang-jin Moon
发明人： Hee-sook Park , Gil-heyun Choi , Sang-bum Kang , Seong-geon Park , Kwang-jin Moon
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/2855 , H01L21/28556 , H01L21/76846 , H01L21/76855 , H01L21/76858
摘要： A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact hole while forming a titanium layer on the cobalt layer. A plug is formed on the titanium layer so as to fill the contact hole.

9. 发明授权

US07067417B2 Methods of removing resistive remnants from contact holes using silicidation 有权
标题翻译：使用硅化物从接触孔去除电阻残留物的方法
公开(公告)号：US07067417B2
公开(公告)日：2006-06-27
申请号：US10881642
申请日：2004-06-30
申请人： Hee-sook Park , Gil-heyun Choi , Jong-myeong Lee
发明人： Hee-sook Park , Gil-heyun Choi , Jong-myeong Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/02052 , H01L21/02063 , H01L21/31116 , H01L21/32134 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L21/76844 , H01L21/76855 , H01L21/76867 , H01L21/76889 , H01L21/76897 , H01L27/10855 , Y10S438/906
摘要： A contact hole can be formed in an insulating layer to expose a surface of an underlying silicon layer at a bottom of the contact hole having a first size. A metal silicide layer can be formed beneath the bottom of the contact hole and removed to form a void beneath the contact hole having a second size that is greater than the first size.
摘要翻译：可以在绝缘层中形成接触孔，以在具有第一尺寸的接触孔的底部露出下面的硅层的表面。可以在接触孔的底部下方形成金属硅化物层，并移除以在接触孔下方形成具有大于第一尺寸的第二尺寸的空隙。

10. 发明授权

US07223689B2 Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer 有权
标题翻译：在形成阻挡金属层的同时形成欧姆层的半导体器件中形成金属接触的方法
公开(公告)号：US07223689B2
公开(公告)日：2007-05-29
申请号：US11112356
申请日：2005-04-22
申请人： Hee-sook Park , Gil-heyun Choi , Sang-bum Kang , Seong-geon Park , Kwang-jin Moon
发明人： Hee-sook Park , Gil-heyun Choi , Sang-bum Kang , Seong-geon Park , Kwang-jin Moon
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/2855 , H01L21/28556 , H01L21/76846 , H01L21/76855 , H01L21/76858
摘要： A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact hole while forming a titanium layer on the cobalt layer. A plug is formed on the titanium layer so as to fill the contact hole.
摘要翻译：通过在硅衬底上形成具有接触孔的绝缘层，形成半导体器件中的金属接触。钴层形成在接触孔的底壁和内壁上。在钴层上形成钛层的同时，在接触孔的底部形成钴硅化物层。在钛层上形成插塞以填充接触孔。

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