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21. 发明授权

US6034893A Non-volatile memory cell having dual avalanche injection elements 有权
标题翻译：具有双雪崩注入元件的非易失性存储单元
公开(公告)号：US6034893A
公开(公告)日：2000-03-07
申请号：US334052
申请日：1999-06-15
申请人： Sunil D. Mehta
发明人： Sunil D. Mehta
IPC分类号： G11C16/04 , H01L21/8247 , H01L29/861
CPC分类号： H01L29/8616 , G11C16/0441 , H01L27/11521 , H01L27/11558
摘要： A non-volatile memory cell includes a well region formed in a semiconductor substrate. First and second avalanche injection elements reside in the well region. A bifurcated floating-gate electrode includes a first segment overlying the first avalanche injection element and a second segment overlying the second avalanche injection element. A first contact region resides in the well region adjacent to the first segment of the floating-gate electrode, and a second contact region resides in the well region adjacent to the second segment of the floating-gate electrode. Upon the application of programming or erasing voltage, electrical charge is independently transferred to each of the first and second segments of the floating-gate electrode from the first and second avalanche injection elements, respectively.
摘要翻译：非易失性存储单元包括形成在半导体衬底中的阱区。第一和第二雪崩注入元件驻留在井区域中。分叉浮栅电极包括覆盖第一雪崩注入元件的第一段和覆盖第二雪崩注入元件的第二段。第一接触区域位于与浮栅电极的第一段相邻的阱区中，并且第二接触区位于与浮栅电极的第二段相邻的阱区中。在施加编程或擦除电压时，电荷分别独立地从第一和第二雪崩注入元件转移到浮栅电极的第一和第二段中的每一个。

22. 发明授权

US5162880A Nonvolatile memory cell having gate insulation film with carrier traps therein 失效
标题翻译：具有栅极绝缘膜的非易失性存储单元，其中具有载流子阱
公开(公告)号：US5162880A
公开(公告)日：1992-11-10
申请号：US589436
申请日：1990-09-27
申请人： Hiroaki Hazama , Kazumi Nishinohara
发明人： Hiroaki Hazama , Kazumi Nishinohara
IPC分类号： H01L27/115 , H01L29/861
CPC分类号： H01L29/8616 , H01L27/115
摘要： A nonvolatile memory cell comprises a semiconductor substrate of first conduction type, a high-concentration impurity region of second conduction type formed on the semiconductor substrate and connected to a bit line, an insulation film in which carrier traps are formed, and a gate electrode that is opposite the high-concentration impurity region across the insulation film and connected to a word line. Carriers are captured by, and released from, the carrier traps formed in the insulation film, in response to bias voltages applied to the word and bit lines. Information stored in the memory cell depends on whether or not the carrier traps are holding carriers. The information is read out of the memory cell as the difference of a tunneling current flowing between the semiconductor substrate and the high-concentration impurity region.
摘要翻译：非易失性存储单元包括：第一导电类型的半导体衬底，形成在半导体衬底上并连接到位线的第二导电类型的高浓度杂质区域，其中形成载流子阱的绝缘膜;以及栅电极，与绝缘膜上的高浓度杂质区相对并连接到字线。响应于施加到字和位线的偏置电压，承载体被捕获并从其中形成的载流子捕集阱释放。存储在存储器单元中的信息取决于载波陷阱是否是保持载波。该信息作为在半导体衬底和高浓度杂质区域之间流动的隧道电流的差异从存储单元中读出。

23. 发明授权

US09559110B2 Dense arrays and charge storage devices 有权
标题翻译：密集阵列和电荷存储设备
公开(公告)号：US09559110B2
公开(公告)日：2017-01-31
申请号：US14856131
申请日：2015-09-16
申请人： SANDISK 3D LLC
发明人： Thomas H. Lee
IPC分类号： H01L29/00 , H01L27/115 , G11C16/34 , H01L21/822 , H01L27/06 , H01L27/112 , H01L29/423 , H01L29/66 , H01L29/788 , H01L29/792 , H01L29/861 , H01L29/16 , G11C16/10 , G11C16/14 , G11C16/26 , H01L29/06 , H01L29/51 , H01L27/12
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包含多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续级之间的至少一个表面平坦化。

24. 发明授权

US08823076B2 Dense arrays and charge storage devices 有权
标题翻译：密集阵列和电荷存储设备
公开(公告)号：US08823076B2
公开(公告)日：2014-09-02
申请号：US14227425
申请日：2014-03-27
申请人： SanDisk 3D LLC
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald
IPC分类号： H01L29/792 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

25. 发明申请

US20140217491A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 有权
公开(公告)号：US20140217491A1
公开(公告)日：2014-08-07
申请号：US14227425
申请日：2014-03-27
申请人： SANDISK 3D LLC
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

26. 发明申请

US20140167134A1 SELF-ALIGNED VERTICAL NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：自对准垂直非线性半导体存储器件
公开(公告)号：US20140167134A1
公开(公告)日：2014-06-19
申请号：US13514032
申请日：2012-02-02
申请人： Pengfei Wang , Xi Lin , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Xi Lin , Qingqing Sun , Wei Zhang
IPC分类号： H01L27/115
CPC分类号： H01L27/11563 , G11C16/0475 , H01L21/84 , H01L27/1021 , H01L27/1026 , H01L27/1157 , H01L27/1203 , H01L29/7391 , H01L29/7923 , H01L29/8616
摘要： The present invention belongs to the technical field of semiconductor memory devices and specifically relates to a self-aligned vertical nonvolatile semiconductor memory device, Including: a semiconductor substrate, a drain region of a first doping type, two source regions of a second doping type, a stacked gate used to capture electrons; wherein the drain region, the two source regions and the stacked gate form two tunneling field effect transistors (TFETs) sharing one gate and one drain, the drain region current of each of the TFET is affected by the quantity and distribution of the charges in the stacked gate used to capture electrons, the drain is buried in the semiconductor substrate, the source regions above the drain region are separated from the drain through a channel and separated form each other through a region of the first doping type. The semiconductor memory device of the present invention features small unit area and simple manufacturing process. The memory chip using the present invention is of low manufacturing cost and high storage density.
摘要翻译：本发明属于半导体存储器件的技术领域，具体涉及一种自对准的垂直非易失性半导体存储器件，包括：半导体衬底，第一掺杂类型的漏极区域，第二掺杂型的两个源极区域，用于捕获电子的堆叠栅; 其中漏极区域，两个源极区域和堆叠的栅极形成共享一个栅极和一个漏极的两个隧道场效应晶体管（TFET），每个TFET的漏极区域电流受到电荷的量和分布的影响用于捕获电子的堆叠栅极，漏极埋在半导体衬底中，漏极区域上方的源极区域通过沟道与漏极分离，并通过第一掺杂类型的区域彼此分离。本发明的半导体存储器件具有小的单位面积和简单的制造工艺。使用本发明的存储芯片的制造成本低，存储密度高。

27. 发明授权

US08729616B2 Low leakage capacitor for analog floating-gate integrated circuits 有权
标题翻译：用于模拟浮栅集成电路的低漏电容
公开(公告)号：US08729616B2
公开(公告)日：2014-05-20
申请号：US13718485
申请日：2012-12-18
申请人： Texas Instruments Incorporated
发明人： Imran Mahmood Khan , Allan T. Mitchell , Kaiping Liu
IPC分类号： H01L29/94
CPC分类号： H01L29/94 , G11C27/005 , G11C2216/10 , H01L27/1156 , H01L27/11803 , H01L28/40 , H01L28/60 , H01L29/7883 , H01L29/8616
摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.
摘要翻译：集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。模拟浮栅电极形成为多晶硅栅极电平，并且包括用作晶体管栅电极的部分，金属对多晶硅存储电容器的板以及多至多晶硅隧道电容器的板。硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。

28. 发明授权

US08574958B2 Method for manufacturing a gate-control diode semiconductor memory device 有权
标题翻译：栅极控制二极管半导体存储器件的制造方法
公开(公告)号：US08574958B2
公开(公告)日：2013-11-05
申请号：US13535032
申请日：2012-06-27
申请人： Pengfei Wang , Xiaoyong Liu , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Xiaoyong Liu , Qingqing Sun , Wei Zhang
IPC分类号： H01L21/00
CPC分类号： H01L29/7391 , H01L29/8616
摘要： This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor storage device. When the floating gate voltage is relatively high, the channel under the floating gate is of n type and a simple gate-control pn junction structure is configured; by controlling effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through a floating gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed while the quantity of charges in the floating gate determines the device threshold voltage, thus realizing memory functions. This invention features capacity of manufacturing gate-control diode memory devices able to reduce the chip power consumption through advantages of high driving current and small sub-threshold swing. This invention is applicable to semiconductor devices manufacturing based on flexible substrate and flat panel displays and floating gate memories, etc.
摘要翻译：本发明属于半导体器件制造领域，并且公开了一种用于制造栅极控制二极管半导体存储器件的方法。当浮动栅极电压相对较高时，浮动栅极下的沟道为n型，并配置了简单的栅极控制pn结结构; 通过背栅控制来控制ZnO膜的有效n型浓度，通过浮栅将n型ZnO反转为p型，并使用NiO作为p型半导体，形成npnp掺杂结构，浮动门中的电荷决定了器件的阈值电压，从而实现了存储器的功能。本发明具有制造栅极控制二极管存储器件的能力，其能够通过高驱动电流和小的次级阈值摆动的优点来降低芯片功耗。本发明适用于基于柔性基板和平板显示器和浮动栅极存储器等的半导体器件制造。

29. 发明授权

US08466505B2 Multi-level flash memory cell capable of fast programming 有权
标题翻译：能够快速编程的多级闪存单元
公开(公告)号：US08466505B2
公开(公告)日：2013-06-18
申请号：US11077479
申请日：2005-03-10
申请人： Li-Shyue Lai , Hung-Wei Chen , Wen-Chin Lee , Min-Hwa Chi
发明人： Li-Shyue Lai , Hung-Wei Chen , Wen-Chin Lee , Min-Hwa Chi
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L29/66825 , H01L29/7391 , H01L29/8616
摘要： A semiconductor device and a method of forming the same. The semiconductor device comprises a gate structure comprising a tunnel oxide over a substrate; a floating gate over the tunnel oxide; a dielectric over the floating gate; and a control gate over the dielectric. The semiconductor device further comprises: spacers along opposite edges of the gate structure; a first impurity region doped with a first type of dopant laterally spaced apart from a first edge of the gate structure; and a second impurity region doped with a second type of dopant, opposite from the first type, the drain being substantially under the drain spacer and substantially aligned with a second edge of the gate structure.
摘要翻译：一种半导体器件及其制造方法。半导体器件包括栅极结构，其包括在衬底上的隧道氧化物; 隧道氧化物上的浮动栅; 在浮动栅极上的电介质; 以及电介质上的控制栅极。半导体器件还包括：沿着栅极结构的相对边缘的间隔物; 掺杂有与栅极结构的第一边缘横向间隔开的第一类型掺杂物的第一杂质区; 以及掺杂有与第一类型相反的第二类型掺杂剂的第二杂质区，漏极基本上在漏极间隔下方并且基本上与栅极结构的第二边缘对准。

30. 发明申请

US20120261740A1 FLASH MEMORY AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：闪存及其制造方法
公开(公告)号：US20120261740A1
公开(公告)日：2012-10-18
申请号：US13389720
申请日：2011-10-14
申请人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , Shenghu Tan
发明人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , Shenghu Tan
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7391 , H01L27/1203 , H01L29/788 , H01L29/8616
摘要： The present invention discloses a flash memory and a method for fabricating the same, and relates to the technical field of the semiconductor memory. The flash memory includes a buried oxygen layer on which a source terminal, a channel, and a drain terminal are disposed, wherein the channel is between the source terminal and the drain terminal, and a tunneling oxide layer, a polysilicon floating gate, a blocking oxide layer, and a polysilicon control gate are sequentially disposed on the channel, and a thin silicon nitride layer is disposed between the source terminal and the channel. The method includes: 1) performing a shallow trench isolation on a SOI silicon substrate to form an active region; 2) sequentially forming a tunneling oxide layer and a first polysilicon layer on the SOI silicon substrate to form a polysilicon floating gate, and forming a blocking oxide layer and a second polysilicon layer to form a polysilicon control gate; 3) etching the resultant structure to form a gate stack structure; 4) forming a drain terminal at one side of the gate stack structure, etching the silicon film at the other side of the gate stack structure, growing a thin silicon nitride layer, and then refilling the hole structure with silicon material, to form a source terminal. The method has the advantages of high programming efficiency, low power consumption, effectively preventing source-drain punchthrough effect.
摘要翻译：本发明公开了一种闪速存储器及其制造方法，涉及半导体存储器的技术领域。闪速存储器包括掩埋氧层，其上设置有源极端子，沟道和漏极端子，其中沟道位于源极端子和漏极端子之间，以及隧道氧化物层，多晶硅浮动栅极，阻塞层氧化物层和多晶硅控制栅极依次设置在沟道上，并且在源极端子和沟道之间设置有薄的氮化硅层。该方法包括：1）在SOI硅衬底上进行浅沟槽隔离以形成有源区; 2）在SOI硅衬底上依次形成隧道氧化物层和第一多晶硅层，以形成多晶硅浮栅，并形成阻挡氧化层和第二多晶硅层以形成多晶硅控制栅极; 3）蚀刻所得结构以形成栅叠层结构; 4）在栅极堆叠结构的一侧形成漏极端子，蚀刻栅极叠层结构的另一侧的硅膜，生长薄的氮化硅层，然后用硅材料再填充孔结构，以形成源极终奌站。该方法具有编程效率高，功耗低，有效防止源极漏极穿通效应的优点。

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