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1. 发明授权

US09698202B2 Parallel bit line three-dimensional resistive random access memory 有权
公开(公告)号：US09698202B2
公开(公告)日：2017-07-04
申请号：US14635419
申请日：2015-03-02
申请人： SANDISK 3D LLC
发明人： Seje Takaki
IPC分类号： H01L27/24 , G11C13/00 , H01L45/00
CPC分类号： H01L27/249 , G11C13/0007 , G11C13/0069 , G11C13/0097 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/141 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： Resistive random access memory (ReRAM) array includes line stack structures located over a substrate. The line stack structures are laterally spaced apart along a first horizontal direction, and extend along a second horizontal direction that is different from the first horizontal direction. Each line stack structure comprises an alternating plurality of word lines and bit lines. An intervening line stack including a memory material line structure, an intrinsic semiconductor material line structure, and a doped semiconductor material line structure is located between each vertically neighboring pair of a word line and a bit line within the alternating plurality of word lines and bit lines. A two-dimensional array of vertical selector lines functions as gate electrodes that activates a semiconductor channel between a word line and a bit line. Resistance of the memory material line structure contacting the activated semiconductor channel can be programmed and/or measured within the ReRAM array.

2. 发明授权

US09653617B2 Multiple junction thin film transistor 有权
公开(公告)号：US09653617B2
公开(公告)日：2017-05-16
申请号：US14723038
申请日：2015-05-27
申请人： SanDisk 3D LLC
发明人： Guangle Zhou , Ming-Che Wu , Yung-Tin Chen
IPC分类号： H01L29/786 , H01L27/24 , H01L29/423 , H01L29/66 , H01L21/265 , H01L45/00
CPC分类号： H01L29/78696 , H01L21/26513 , H01L21/2652 , H01L27/2454 , H01L27/249 , H01L29/42392 , H01L29/66742 , H01L29/78642 , H01L45/16
摘要： A multiple junction thin film transistor (TFT) is disclosed. The body of the TFT may have an n+ layer residing in a p− region of the body. The TFT may have an n+ source and an n+ drain on either side of the p− region of the body. Thus, the TFT has an n+/p−/n+/p−/n+ structure in this example. The n+ layer in the p− region increases the breakdown voltage. Also, drive current is increased. The impurity concentration in the n+ layer in the p− body and/or thickness of the n+ layer in the p− body may be tuned to increase performance of the TFT. In an alternative, the body of the TFT has a p+ layer residing in an n− region of the body. The TFT may have a p+ source and a p+ drain on either side of the p− region of the body.

3. 发明授权

US09646880B1 Monolithic three dimensional memory arrays formed using sacrificial polysilicon pillars 有权
公开(公告)号：US09646880B1
公开(公告)日：2017-05-09
申请号：US14995224
申请日：2016-01-14
申请人： SanDisk 3D LLC
发明人： Seje Takaki , Teruyuki Mine
IPC分类号： H01L21/768 , H01L27/115 , H01L21/28 , H01L21/283
CPC分类号： H01L21/76877 , H01L21/28273 , H01L21/28282 , H01L21/283 , H01L27/115 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/16
摘要： A method is provided for forming a monolithic three-dimensional memory array. The method includes forming a first vertically-oriented polysilicon pillar above a substrate, the first vertically-oriented polysilicon pillar surrounded by a dielectric material, removing the first vertically-oriented polysilicon pillar to form a first void in the dielectric material, and filling the first void with a conductive material to form a first via.

4. 发明申请

US20170125483A1 RERAM MIM STRUCTURE FORMATION 审中-公开
公开(公告)号：US20170125483A1
公开(公告)日：2017-05-04
申请号：US14928999
申请日：2015-10-30
申请人： SANDISK 3D LLC
发明人： Yoichiro Tanaka
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2418 , H01L27/2454 , H01L27/2481 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1683
摘要： Methods for improving the operation of a memory array by arranging a Metal-Insulator-Metal (MIM) structure between a word line and an adjustable resistance bit line structure are described. The MIM structure may correspond with a metal/ReRAM material/metal structure that is arranged between the word line and an intrinsic polysilicon region of the adjustable resistance bit line structure. In one example, a word line (e.g., TiN) may be arranged adjacent to a ReRAM material (e.g., HfOx) that is adjacent to a first metal (e.g., TiN) that is adjacent to the intrinsic polysilicon region. The first metal may comprise a metal, metal-nitride, or a metal-silicide. In another example, the word line may be arranged adjacent to a ReRAM material that is adjacent to a first metal (e.g., TiN) that is adjacent to a second metal different from the first metal (e.g., tungsten) that is adjacent to the intrinsic polysilicon region.

5. 发明授权

US09627009B2 Interleaved grouped word lines for three dimensional non-volatile storage 有权
公开(公告)号：US09627009B2
公开(公告)日：2017-04-18
申请号：US14341519
申请日：2014-07-25
申请人： SANDISK 3D LLC
发明人： Christopher J. Petti
IPC分类号： G11C5/02 , G11C13/00
CPC分类号： G11C5/02 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0083 , G11C2213/71
摘要： A three dimensional non-volatile storage system includes a substrate and a plurality of memory cells arranged in a monolithic three dimensional memory array (or other 3D structure) positioned above and not in the substrate. The system includes a plurality of vertical bit lines and a plurality of word lines. Each group of three neighboring word lines on a common level of the three dimensional memory array are electrically isolated from each other and at least a subset of the three neighboring word lines of each group are connected to other word lines.

6. 发明申请

US20170077184A1 THREE-DIMENSIONAL RESISTIVE RANDOM ACCESS MEMORY CONTAINING SELF-ALIGNED MEMORY ELEMENTS 审中-公开
标题翻译：包含自对准存储元件的三维电阻随机存取存储器
公开(公告)号：US20170077184A1
公开(公告)日：2017-03-16
申请号：US14851296
申请日：2015-09-11
申请人： SanDisk 3D LLC
发明人： Shin KIKUCHI , Kazushi KOMEDA , Takuya FUTASE , Teruyuki MINE , Seje TAKAKI , Eiji HAYASHI , Toshihide TOBITSUKA
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2481 , H01L27/2436 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1616 , H01L45/1633
摘要： An alternating material stack of insulator lines and first electrically conductive material layers is formed over a substrate, and is patterned to provide alternating stacks of insulating layers and first electrically conductive lines. A metal can be selectively deposited on the physically exposed sidewalls of the first electrically conductive material layers to form metal lines, while not growing from the surfaces of the insulator lines. The metal lines are oxidized to form metal oxide lines that are self-aligned to the sidewalls of the first electrically conductive lines. Vertically extending second electrically conductive lines can be formed as a two-dimensional array of generally pillar-shaped structures between the alternating stacks of the insulator lines and the first electrically conductive lines. Each portion of the metal oxide lines at junctions of first and second electrically conductive lines constitute a resistive memory element for a resistive random access memory (ReRAM) device.
摘要翻译：绝缘体线和第一导电材料层的交替材料堆叠形成在衬底上，并被图案化以提供绝缘层和第一导电线的交替堆叠。可以在第一导电材料层的物理暴露的侧壁上选择性地沉积金属以形成金属线，而不会从绝缘体线的表面生长。金属线被氧化以形成与第一导电线的侧壁自对准的金属氧化物线。垂直延伸的第二导电线可以形成为在绝缘体线的交替堆叠和第一导电线之间的大致柱状结构的二维阵列。金属氧化物线在第一和第二导电线的交点处的每个部分构成用于电阻随机存取存储器（ReRAM）器件的电阻性存储元件。

7. 发明授权

US09576660B2 Low forming voltage non-volatile storage device 有权
标题翻译：低成型电压非易失性存储装置
公开(公告)号：US09576660B2
公开(公告)日：2017-02-21
申请号：US14996144
申请日：2016-01-14
申请人： SANDISK 3D LLC
发明人： Zhida Lan , Roy E. Scheuerlein , Tong Zhang , Kun Hou , Perumal Ratnam
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0097 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/52 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.
摘要翻译：存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流被限制。在成形期间，将形成电压施加到存储元件，其极性使得较高的电压被施加到阳极，而较低的电压施加到阴极。

8. 发明授权

US09559110B2 Dense arrays and charge storage devices 有权
标题翻译：密集阵列和电荷存储设备
公开(公告)号：US09559110B2
公开(公告)日：2017-01-31
申请号：US14856131
申请日：2015-09-16
申请人： SANDISK 3D LLC
发明人： Thomas H. Lee
IPC分类号： H01L29/00 , H01L27/115 , G11C16/34 , H01L21/822 , H01L27/06 , H01L27/112 , H01L29/423 , H01L29/66 , H01L29/788 , H01L29/792 , H01L29/861 , H01L29/16 , G11C16/10 , G11C16/14 , G11C16/26 , H01L29/06 , H01L29/51 , H01L27/12
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包含多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续级之间的至少一个表面平坦化。

9. 发明授权

US09543009B2 Multiple layer forming scheme for vertical cross point reram 有权
标题翻译：垂直交叉点多层形成方案
公开(公告)号：US09543009B2
公开(公告)日：2017-01-10
申请号：US14887532
申请日：2015-10-20
申请人： SanDisk 3D LLC
发明人： Chang Siau , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/77
摘要： Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, during a forming operation, a cross-point memory array may be biased such that waste currents are minimized or eliminated. In one example, the memory array may be biased such that a first word line comb is set to a first voltage, a second word line comb interdigitated with the first word line comb is set to the first voltage, and selected vertical bit lines are set to a second voltage such that a forming voltage is applied across non-volatile storage elements to be formed. In some embodiments, a memory array may include a plurality of word line comb layers and a forming operation may be concurrently performed on non-volatile storage elements on all of the plurality of word line comb layers or a subset of the plurality of word line comb layers.
摘要翻译：描述了在非易失性存储系统中形成非易失性存储元件的方法。在一些实施例中，在成形操作期间，可以偏置交叉点存储器阵列，使得浪费电流被最小化或消除。在一个示例中，存储器阵列可以被偏置，使得第一字线梳被设置为第一电压，与第一字线梳交织的第二字线梳被设置为第一电压，并且选择的垂直位线被设置到第二电压，使得在要形成的非易失性存储元件上施加形成电压。在一些实施例中，存储器阵列可以包括多个字线梳状层，并且可以在所有多个字线梳状层上的非易失性存储元件上同时执行形成操作，或者多个字线梳的子集层。

10. 发明授权

US09515023B2 Multilevel contact to a 3D memory array and method of making thereof 有权
标题翻译：与3D存储器阵列的多层接触及其制造方法
公开(公告)号：US09515023B2
公开(公告)日：2016-12-06
申请号：US14643211
申请日：2015-03-10
申请人： SANDISK 3D LLC
发明人： Toshihide Tobitsuka , Seje Takaki
IPC分类号： H01L23/535 , H01L21/768 , H01L27/115 , H01L27/24
CPC分类号： H01L23/535 , H01L21/76895 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L27/2481 , H01L27/249 , H01L2924/0002 , H01L2924/00
摘要： A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate. The plurality of electrically conductive layers form a stepped pattern in the contact region, where each respective electrically insulating layer includes a sidewall and a respective underlying electrically conductive layer in the stack extends laterally beyond the sidewall. Optionally, a plurality of electrically conductive via connections can be formed, which have top surfaces within a same horizontal plane, have bottom surfaces contacting a respective electrically conductive layer located at different levels, and are isolated from one another by at least one trench isolation structure.
摘要翻译：多级设备包括至少一个设备区域和至少一个接触区域。接触区域具有交替的多个导电层和位于衬底上方的多个电绝缘层的堆叠。多个导电层在接触区域中形成阶梯图案，其中每个相应的电绝缘层包括侧壁，并且堆叠中的相应的下面的导电层横向延伸超过侧壁。可选地，可以形成多个导电通孔连接件，其具有在相同水平平面内的顶表面，其底表面接触位于不同水平的相应导电层，并且通过至少一个沟槽隔离结构彼此隔离。

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