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21. 发明申请

US20150278110A1 TRANSPARENT CODE PATCHING 有权
标题翻译：透明代码贴图
公开(公告)号：US20150278110A1
公开(公告)日：2015-10-01
申请号：US14231628
申请日：2014-03-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Michael K. Gschwind
IPC分类号： G06F12/10 , G06F13/16 , G06F12/08 , G06F12/02
CPC分类号： G06F3/061 , G06F3/0619 , G06F3/065 , G06F3/0685 , G06F8/40 , G06F9/00 , G06F9/30174 , G06F9/328 , G06F9/3802 , G06F9/45516 , G06F12/10 , G06F13/1663 , G06F2212/654
摘要： An application located in one or more first memory regions is executed. The application has a separate modified portion, which is located in one or more second memory regions different from the one or more first memory regions. A request is obtained to access one of a first memory region or a second memory region, the request including an address of a first type. Based on obtaining the request, the address is translated to another address. The another address is of a second type and indicates the first memory region or the second memory region. The translating is based on an attribute associated with the address, in which the attribute is used to select information from a plurality of information concurrently available for selection to be used in translating the address. The plurality of information to provide multiple addresses of the second type, one of which is the another address. The another address is used to access the first memory region or the second memory region.
摘要翻译：执行位于一个或多个第一存储器区域中的应用。应用具有单独的修改部分，该部分位于与一个或多个第一存储器区域不同的一个或多个第二存储器区域中。获得访问第一存储器区域或第二存储器区域中的一个的请求，该请求包括第一类型的地址。基于获得请求，地址被转换为另一个地址。另一地址是第二类型，并且指示第一存储器区域或第二存储器区域。翻译是基于与地址相关联的属性，其中该属性用于从同时可用于选择用于翻译地址的多个信息中选择信息。多个信息提供第二类型的多个地址，其中之一是另一个地址。另一地址用于访问第一存储器区域或第二存储器区域。

22. 发明申请

US20150277975A1 Instruction and Logic for a Memory Ordering Buffer 有权
标题翻译：内存订购缓冲区的指令和逻辑
公开(公告)号：US20150277975A1
公开(公告)日：2015-10-01
申请号：US14229007
申请日：2014-03-28
申请人： John H. Kelm , Denis M. Khartikov , Naveen Neelakantam
发明人： John H. Kelm , Denis M. Khartikov , Naveen Neelakantam
IPC分类号： G06F9/48 , G06F9/30 , G06F12/08
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30174 , G06F9/3808 , G06F9/3822 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： A processor includes an allocator with logic assigning alias hardware resources to instructions within an atomic region of instructions. The atomic region includes reordered instructions. The processor also includes a dispatcher with logic to dispatch instructions from the atomic region of instructions for execution. Furthermore, the processor includes a memory execution unit with logic to populate the memory execution unit with the instructions from the atomic region of instructions including reordered instructions, receive snoop requests and determine whether the snoop request matches memory address data of elements within the memory execution unit, and prevent reassignment of alias hardware resources for any load instructions that are eligible to match the snoop requests.
摘要翻译：处理器包括具有向指令的原子区域内的指令分配别名硬件资源的逻辑的分配器。原子区域包括重新排序的指令。该处理器还包括一个调度器，该调度器具有从用于执行的指令的原子区域分派指令的逻辑。此外，处理器包括具有逻辑的存储器执行单元，该逻辑使用来自包括重新排序的指令，接收窥探请求的指令的原子区域的指令来填充存储器执行单元，并且确定窥探请求是否匹配存储器执行单元内的元素的存储器地址数据，并且防止别名硬件资源重新分配给符合snoop请求的任何加载指令。

23. 发明授权

US09043580B2 Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA) 有权
标题翻译：对不同指令集架构（ISA）的指令访问具有不同组的不同微指令的模型特定寄存器（MSR）
公开(公告)号：US09043580B2
公开(公告)日：2015-05-26
申请号：US13413346
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/30
CPC分类号： G06F9/30174 , G06F9/30076 , G06F9/30101 , G06F9/30112 , G06F9/3017 , G06F9/30189 , G06F9/30196
摘要： A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.
摘要翻译：能够运行x86指令集架构（ISA）机器语言程序和高级RISC机（ARM）ISA机器语言程序的微处理器。微处理器包括指示微处理器当前是否正在获取x86 ISA或ARM ISA机器语言程序的指令的模式指示器。微处理器还包括多个模型专用寄存器（MSR），其控制微处理器操作的方面。当模式指示符指示微处理器当前正在获取x86 ISA机器语言程序指令时，可通过指定MSR的地址的x86 ISA RDMSR / WRMSR指令访问多个MSR中的每一个。当模式指示符指示微处理器当前正在获取ARM ISA机器语言程序指令时，可通过指定MSR的地址的ARM ISA MRRC / MCRR指令访问多个MSR中的每一个。

24. 发明申请

US20150082007A1 REGISTER MAPPING WITH MULTIPLE INSTRUCTION SETS 审中-公开
标题翻译：具有多个指令集的寄存器映射
公开(公告)号：US20150082007A1
公开(公告)日：2015-03-19
申请号：US14548800
申请日：2014-11-20
申请人： ARM Limited
发明人： Glen Andrew HARRIS , James Nolan HARDAGE , Mark Carpenter GLASS
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30098 , G06F9/30112 , G06F9/3012 , G06F9/30174 , G06F9/34 , G06F9/3824 , G06F9/384
摘要： A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.
摘要翻译：处理器核心支持从第一指令集和第二指令集两者执行程序指令。包含架构寄存器的架构寄存器文件18由两个指令集共享。两个指令集使用逻辑寄存器说明符，其中这些逻辑寄存器说明符的至少一些值对应于架构寄存器文件18内的不同结构寄存器。第一指令集的第一解码器4和用于第二指令集的第二解码器6 用于将逻辑寄存器说明符解码为公共寄存器寻址格式。该公共寄存器寻址格式用于向重命名电路10提供寄存器说明符，用于结合物理寄存器文件16和架构寄存器文件18来支持寄存器重命名。

25. 发明授权

US08959632B2 Safely executing an untrusted native code module on a computing device 有权
标题翻译：在计算设备上安全执行不受信任的本地代码模块
公开(公告)号：US08959632B2
公开(公告)日：2015-02-17
申请号：US13787616
申请日：2013-03-06
申请人： Google Inc.
发明人： J. Bradley Chen , Matthew T. Harren , Matthew Papakipos , David C. Sehr , Bennet S. Yee , Gregory Dardyk
IPC分类号： G06F21/00 , G06F9/445 , H04L29/06 , G06F9/30 , G06F21/53 , G06F21/57
CPC分类号： G06F21/51 , G06F9/30174 , G06F9/44589 , G06F21/53 , G06F21/57 , G06F2221/033 , G06F2221/2113 , G06F2221/2119 , H04L29/06884
摘要： A system that safely executes a native code module on a computing device. During operation, the system receives the native code module, which is comprised of untrusted native program code expressed using native instructions in the instruction set architecture associated with the computing device. The system then loads the native code module into a secure runtime environment, and proceeds to execute a set of instructions from the native code module in the secure runtime environment. The secure runtime environment enforces code integrity, control flow integrity, and data integrity for the native code module. Furthermore, the secure runtime environment moderates which resources can be accessed by the native code module on the computing device and/or how these resources can be accessed. By executing the native code module in the secure runtime environment, the system facilitates achieving native code performance for untrusted program code without a significant risk of unwanted side effects.
摘要翻译：一种在计算设备上安全执行本机代码模块的系统。在操作期间，系统接收本地代码模块，其由使用与计算设备相关联的指令集架构中的本地指令表示的不可信的本机程序代码组成。然后，系统将本机代码模块加载到安全运行时环境中，并继续在安全运行时环境中从本机代码模块执行一组指令。安全运行时环境强制本机代码模块的代码完整性，控制流完整性和数据完整性。此外，安全运行时环境调节哪些资源可以由计算设备上的本地代码模块访问和/或如何访问这些资源。通过在安全运行时环境中执行本地代码模块，系统便于实现不可信程序代码的本地代码性能，而不会产生不必要的副作用的重大风险。

26. 发明申请

US20150046910A1 HARDWARE COMPILATION AND/OR TRANSLATION WITH FAULT DETECTION AND ROLL BACK FUNCTIONALITY 审中-公开
标题翻译：硬件编译和/或翻译具有故障检测和滚动功能
公开(公告)号：US20150046910A1
公开(公告)日：2015-02-12
申请号：US14513402
申请日：2014-10-14
申请人： Intel Corporation
发明人： Nicholas Cheng Hwa Chee , Tryggve Fossum , William C. Hasenplaugh
IPC分类号： G06F9/45 , G06F9/38
CPC分类号： G06F8/44 , G06F9/3001 , G06F9/30087 , G06F9/30174 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/462 , G06F11/0751
摘要： Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result. In some embodiments, an execution unit executes instructions of the second language including commit instructions to record execution checkpoint states of registers mapped to architectural registers, and roll-back instructions to restore the registers mapped to architectural registers to previously recorded execution checkpoint states.
摘要翻译：公开了具有故障检测和回滚功能的硬件编译和/或翻译。编译和/或翻译逻辑接收以一种语言编码的程序，并且将该程序编码成包括指令的第二语言，以支持未被编码为程序的原始语言编码的处理器特征。在一个实施例中，执行单元执行包括执行第一操作的操作检查指令的第二语言的指令并记录用于比较的第一操作结果，以及执行第二操作和故障检测操作的操作测试指令通过比较第二操作结果与记录的第一操作结果。在一些实施例中，执行单元执行第二语言的指令，包括提交指令以记录映射到架构寄存器的寄存器的执行检查点状态，以及回滚指令，将映射到架构寄存器的寄存器恢复到先前记录的执行检查点状态。

27. 发明授权

US08954714B2 Processor with cycle offsets and delay lines to allow scheduling of instructions through time 有权
标题翻译：具有循环偏移和延迟线的处理器，以允许通过时间调度指令
公开(公告)号：US08954714B2
公开(公告)日：2015-02-10
申请号：US12698088
申请日：2010-02-01
申请人： Steven Perry
发明人： Steven Perry
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30174 , G06F9/30145 , G06F9/30181 , G06F9/38 , G06F9/3802 , G06F9/3836 , G06F9/3853 , G06F9/3889
摘要： An apparatus includes a processor. The processor includes two memories. The first memory stores one set of instructions. The second memory stores another set of instructions that are longer than the set of instructions in the first memory. An instruction in the set of instructions in the first memory is used as a pointer to a corresponding instruction in the set of instructions in the second memory.
摘要翻译：一种装置包括处理器。处理器包括两个存储器。第一个存储器存储一组指令。第二存储器存储比第一存储器中的指令集长的另一组指令。将第一存储器中的指令集中的指令用作指向第二存储器中的指令集中的对应指令的指针。

28. 发明申请

US20140344554A1 MICROPROCESSOR ACCELERATED CODE OPTIMIZER AND DEPENDENCY REORDERING METHOD 审中-公开
标题翻译：微处理器加速代码优化器和依赖方法
公开(公告)号：US20140344554A1
公开(公告)日：2014-11-20
申请号：US14360280
申请日：2011-11-22
申请人： Soft Machines, Inc.
发明人： Mohammad Abdallah
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30098 , G06F9/30174 , G06F9/3808 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384
摘要： A dependency reordering method. The method includes accessing an input sequence of instructions, initializing three registers, and loading instruction numbers into a first register. The method further includes loading destination register numbers into a second register, broadcasting values from the first register to a position in a third register in accordance with a position number in the second register, overwriting positions in the third register in accordance with position numbers in the second register, and using information in the third register to populate a dependency matrix for grouping dependent instructions from the sequence of instructions.
摘要翻译：依赖关系重新排序方法。该方法包括访问输入的指令序列，初始化三个寄存器，以及将指令编号加载到第一寄存器中。该方法还包括将目的地寄存器号码加载到第二寄存器中，根据第二寄存器中的位置号从第一寄存器广播值到第三寄存器中的位置，根据第二寄存器中的位置号重写第三寄存器中的位置第二寄存器，以及使用第三寄存器中的信息来填充依赖矩阵，用于从指令序列中分组相关指令。

29. 发明授权

US08880901B2 Secure address handling in a processor 有权
标题翻译：处理器中的安全地址处理
公开(公告)号：US08880901B2
公开(公告)日：2014-11-04
申请号：US11439943
申请日：2006-05-25
申请人： Ulrich Drepper
发明人： Ulrich Drepper
IPC分类号： G06F12/14 , G06F9/30 , G06F9/32
CPC分类号： G06F12/1408 , G06F9/3017 , G06F9/30174 , G06F9/322
摘要： An embodiment generally pertains to a method of secure address handling in a processor. The method includes detecting an instruction that implicitly designates a target address and retrieving an encoded location associated with the target address. The method also includes decoding the encoded location to determine the target address. Another embodiment generally relates to detecting an instruction having an operand designating an encoded target address and determining a location of a target instruction associated with the target address. The method also includes determining a location of a subsequent instruction and encoding the location of the subsequent instruction. The method further includes storing the encoded location of the subsequent instruction.
摘要翻译：实施例通常涉及处理器中的安全地址处理的方法。该方法包括检测隐含地指定目标地址并检索与目标地址相关联的编码位置的指令。该方法还包括解码编码位置以确定目标地址。另一实施例通常涉及检测具有指定编码的目标地址的操作数的指令，并且确定与目标地址相关联的目标指令的位置。该方法还包括确定后续指令的位置并对后续指令的位置进行编码。该方法还包括存储随后指令的编码位置。

30. 发明申请

US20140310505A1 COMPRESSED INSTRUCTION FORMAT 审中-公开
标题翻译：压缩指令格式
公开(公告)号：US20140310505A1
公开(公告)日：2014-10-16
申请号：US14307468
申请日：2014-06-17
申请人： Robert Valentine , Doron Orenstein , Brett L. Toll
发明人： Robert Valentine , Doron Orenstein , Brett L. Toll
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/30174 , G06F9/30178 , G06F9/30185 , G06F9/3816 , G06F9/382
摘要： A technique for decoding an instruction in a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set extensions are supported, and increased functionality is provided, without expanding the code size and, in some cases, reducing the code size.
摘要翻译：一种解码可变长度指令集中的指令的技术。在一个实施例中，描述了指令编码，其中支持遗留，现在和将来的指令集扩展，并且提供增加的功能，而不扩展代码大小，并且在一些情况下减少代码大小。

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