专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140310505A1 COMPRESSED INSTRUCTION FORMAT 审中-公开
标题翻译：压缩指令格式
公开(公告)号：US20140310505A1
公开(公告)日：2014-10-16
申请号：US14307468
申请日：2014-06-17
申请人： Robert Valentine , Doron Orenstein , Brett L. Toll
发明人： Robert Valentine , Doron Orenstein , Brett L. Toll
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/30174 , G06F9/30178 , G06F9/30185 , G06F9/3816 , G06F9/382
摘要： A technique for decoding an instruction in a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set extensions are supported, and increased functionality is provided, without expanding the code size and, in some cases, reducing the code size.
摘要翻译：一种解码可变长度指令集中的指令的技术。在一个实施例中，描述了指令编码，其中支持遗留，现在和将来的指令集扩展，并且提供增加的功能，而不扩展代码大小，并且在一些情况下减少代码大小。

2. 发明授权

US09569208B2 Compressed instruction format 有权
标题翻译：压缩指令格式
公开(公告)号：US09569208B2
公开(公告)日：2017-02-14
申请号：US14307468
申请日：2014-06-17
申请人： Robert Valentine , Doron Orenstein , Brett L. Toll
发明人： Robert Valentine , Doron Orenstein , Brett L. Toll
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/30174 , G06F9/30178 , G06F9/30185 , G06F9/3816 , G06F9/382
摘要： A technique for decoding an instruction in a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set extensions are supported, and increased functionality is provided, without expanding the code size and, in some cases, reducing the code size.
摘要翻译：一种解码可变长度指令集中的指令的技术。在一个实施例中，描述了指令编码，其中支持遗留，现在和将来的指令集扩展，并且提供增加的功能，而不扩展代码大小，并且在一些情况下减少代码大小。

3. 发明申请

US20140189308A1 METHODS, APPARATUS, INSTRUCTIONS, AND LOGIC TO PROVIDE VECTOR ADDRESS CONFLICT DETECTION FUNCTIONALITY 有权
标题翻译：方法，装置，说明和逻辑提供矢量地址冲突检测功能
公开(公告)号：US20140189308A1
公开(公告)日：2014-07-03
申请号：US13731006
申请日：2012-12-29
申请人： Christopher J. Hughes , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Brett L. Toll , Mark J. Charney , Milind B. Girkar
发明人： Christopher J. Hughes , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Brett L. Toll , Mark J. Charney , Milind B. Girkar
IPC分类号： G06F9/30
CPC分类号： G06F9/30021 , G06F9/30018 , G06F9/30036 , G06F9/30109 , G06F9/30145 , G06F9/30185 , G06F9/3838 , G06F9/3887
摘要： Instructions and logic provide SIMD address conflict detection functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store an offset for a data element in a memory. A destination register has corresponding data fields, each of these data fields to store a variable second plurality of bits to store a conflict mask having a mask bit for each offset. Responsive to decoding a vector conflict instruction, execution units compare the offset in each data field with every less significant data field to determine if they hold a matching offset, and in corresponding conflict masks in the destination register, set any mask bits corresponding to a less significant data field with a matching offset. Vector address conflict detection can be used with variable sized elements and to generate conflict masks to resolve dependencies in gather-modify-scatter SIMD operations.
摘要翻译：指令和逻辑提供SIMD地址冲突检测功能。一些实施例包括具有可变多个数据字段的寄存器的处理器，每个数据字段存储用于存储器中的数据元素的偏移量。目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储可变的第二多个位以存储具有每个偏移的掩码位的冲突掩码。响应于对向量冲突指令进行解码，执行单元将每个数据字段中的偏移量与每个较不重要的数据字段进行比较，以确定它们是否保持匹配的偏移，并且在目标寄存器中的相应冲突掩码中，设置对应于较少具有匹配偏移的重要数据字段。向量地址冲突检测可以与可变大小的元素一起使用，并生成冲突掩码来解决收集修改分散SIMD操作中的依赖关系。

4. 发明申请

US20140189307A1 METHODS, APPARATUS, INSTRUCTIONS, AND LOGIC TO PROVIDE VECTOR ADDRESS CONFLICT RESOLUTION WITH VECTOR POPULATION COUNT FUNCTIONALITY 有权
标题翻译：方法，设备，说明和逻辑提供向量地址冲突分解与向量人口计数功能
公开(公告)号：US20140189307A1
公开(公告)日：2014-07-03
申请号：US13731005
申请日：2012-12-29
申请人： Robert Valentine , Mark J. Charney , Jesus Corbal , Milind B. Girkar , Christopher J. Hughes , Elmoustapha Ould-Ahmed-Vall , Brett L. Toll
发明人： Robert Valentine , Mark J. Charney , Jesus Corbal , Milind B. Girkar , Christopher J. Hughes , Elmoustapha Ould-Ahmed-Vall , Brett L. Toll
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F7/607 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3836 , G06F9/3887 , H03M7/20
摘要： Instructions and logic provide SIMD address conflict resolution with vector population count functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store a variable second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of bits set to one for corresponding data fields. Responsive to decoding a vector population count instruction, execution units count the number of bits set to one for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector population count instructions can be used with variable sized elements and conflict masks to generate iteration counts and completion masks to be used each iteration to resolve dependencies in gather-modify-scatter SIMD operations.
摘要翻译：指令和逻辑提供SIMD地址冲突解决与向量群体计数功能。一些实施例包括具有可变多个数据字段的寄存器的处理器，每个数据字段用于存储可变的第二多个位。目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储为相应的数据字段设置为1的位数的计数。响应于对向量群体计数指令进行解码，执行单元对寄存器中的每个数据字段设置为1的位数进行计数，并将计数存储在第一目的地寄存器的相应数据字段中。矢量人口计数指令可用于可变大小的元素和冲突掩码，以生成迭代计数和完成掩码，以便在每次迭代中使用以解决聚集修改散射SIMD操作中的依赖关系。

5. 发明授权

US08078836B2 Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits 有权
标题翻译：在多个通道上操作的矢量洗牌指令，每个通道具有使用公共的每通道控制位的多个数据元素
公开(公告)号：US08078836B2
公开(公告)日：2011-12-13
申请号：US11967211
申请日：2007-12-30
申请人： Zeev Sperber , Robert Valentine , Benny Eitan , Doron Orenstein
发明人： Zeev Sperber , Robert Valentine , Benny Eitan , Doron Orenstein
IPC分类号： G06F15/16
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/3885 , G06F9/3887
摘要： In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands having corresponding lanes, each lane divided into corresponding portions of multiple data elements. Sets of data elements are selected from corresponding portions of every lane of the source operand according to per-lane control bits. Elements of these sets are copied to specified fields in corresponding portions of every lane of the destination operand. Another embodiment of the shuffle instruction also specifies a second source operand, all operands having corresponding lanes divided into multiple data elements. A set selected according to per-lane control bits contains data elements from every lane portion of a first source operand and data elements from every corresponding lane portion of the second source operand. Set elements are copied to specified fields in every lane of the destination operand.
摘要翻译：描述车道内向量随机操作。在一个实施例中，混洗指令指定每通道控制位，源操作数和目的地操作数的字段，这些操作数具有相应的通道，每个通道被划分为多个数据元素的相应部分。根据每通道控制位，从源操作数的每个通道的相应部分中选择数据元素的集合。这些集合的元素被复制到目标操作数的每个通道的相应部分中的指定字段。混洗指令的另一实施例还指定第二源操作数，所有操作数具有被划分为多个数据元素的相应通道。根据每通道控制位选择的集合包含来自第一源操作数的每个通道部分的数据元素和来自第二源操作数的每个对应通道部分的数据元素。将元素复制到目标操作数的每个通道中的指定字段。

6. 发明授权

US08914613B2 Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits 有权
标题翻译：在多个通道上操作的矢量洗牌指令，每个通道使用相同的每通道控制位集合具有多个数据元素
公开(公告)号：US08914613B2
公开(公告)日：2014-12-16
申请号：US13219418
申请日：2011-08-26
申请人： Zeev Sperber , Robert Valentine , Benny Eitan , Doron Orenstein
发明人： Zeev Sperber , Robert Valentine , Benny Eitan , Doron Orenstein
IPC分类号： G06F15/16 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/3885 , G06F9/3887
摘要： In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands having corresponding lanes, each lane divided into corresponding portions of multiple data elements. Sets of data elements are selected from corresponding portions of every lane of the source operand according to per-lane control bits. Elements of these sets are copied to specified fields in corresponding portions of every lane of the destination operand. Another embodiment of the shuffle instruction also specifies a second source operand, all operands having corresponding lanes divided into multiple data elements. A set selected according to per-lane control bits contains data elements from every lane portion of a first source operand and data elements from every corresponding lane portion of the second source operand. Set elements are copied to specified fields in every lane of the destination operand.
摘要翻译：描述车道内向量随机操作。在一个实施例中，混洗指令指定每通道控制位，源操作数和目的地操作数的字段，这些操作数具有相应的通道，每个通道被划分为多个数据元素的相应部分。根据每通道控制位，从源操作数的每个通道的相应部分中选择数据元素的集合。这些集合的元素被复制到目标操作数的每个通道的相应部分中的指定字段。混洗指令的另一实施例还指定第二源操作数，所有操作数具有被划分为多个数据元素的相应通道。根据每通道控制位选择的集合包含来自第一源操作数的每个通道部分的数据元素和来自第二源操作数的每个对应通道部分的数据元素。将元素复制到目标操作数的每个通道中的指定字段。

7. 发明申请

US20130212360A1 In-Lane Vector Shuffle Instructions 审中-公开
标题翻译：内线向量随机指令
公开(公告)号：US20130212360A1
公开(公告)日：2013-08-15
申请号：US13838048
申请日：2013-03-15
申请人： Zeev Sperber , Robert Valentine , Benny Eitan , Doron Orenstein
发明人： Zeev Sperber , Robert Valentine , Benny Eitan , Doron Orenstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/3885 , G06F9/3887
摘要： In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands having corresponding lanes, each lane divided into corresponding portions of multiple data elements. Sets of data elements are selected from corresponding portions of every lane of the source operand according to per-lane control bits. Elements of these sets are copied to specified fields in corresponding portions of every lane of the destination operand. Another embodiment of the shuffle instruction also specifies a second source operand, all operands having corresponding lanes divided into multiple data elements. A set selected according to per-lane control bits contains data elements from every lane portion of a first source operand and data elements from every corresponding lane portion of the second source operand. Set elements are copied to specified fields in every lane of the destination operand.
摘要翻译：描述车道内向量随机操作。在一个实施例中，混洗指令指定每通道控制位，源操作数和目的地操作数的字段，这些操作数具有相应的通道，每个通道被划分为多个数据元素的相应部分。根据每通道控制位，从源操作数的每个通道的相应部分中选择数据元素的集合。这些集合的元素被复制到目标操作数的每个通道的相应部分中的指定字段。混洗指令的另一实施例还指定第二源操作数，所有操作数具有被划分为多个数据元素的相应通道。根据每通道控制位选择的集合包含来自第一源操作数的每个通道部分的数据元素和来自第二源操作数的每个对应通道部分的数据元素。将元素复制到目标操作数的每个通道中的指定字段。

8. 发明申请

US20090172358A1 IN-LANE VECTOR SHUFFLE INSTRUCTIONS 有权
标题翻译：在线路向量小指示
公开(公告)号：US20090172358A1
公开(公告)日：2009-07-02
申请号：US11967211
申请日：2007-12-30
申请人： ZEEV SPERBER , Robert Valentine , Benny Eitan , Doron Orenstein
发明人： ZEEV SPERBER , Robert Valentine , Benny Eitan , Doron Orenstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/3885 , G06F9/3887
摘要： In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands having corresponding lanes, each lane divided into corresponding portions of multiple data elements. Sets of data elements are selected from corresponding portions of every lane of the source operand according to per-lane control bits. Elements of these sets are copied to specified fields in corresponding portions of every lane of the destination operand. Another embodiment of the shuffle instruction also specifies a second source operand, all operands having corresponding lanes divided into multiple data elements. A set selected according to per-lane control bits contains data elements from every lane portion of a first source operand and data elements from every corresponding lane portion of the second source operand. Set elements are copied to specified fields in every lane of the destination operand.
摘要翻译：描述车道内向量随机操作。在一个实施例中，混洗指令指定每通道控制位，源操作数和目的地操作数的字段，这些操作数具有相应的通道，每个通道被划分为多个数据元素的相应部分。根据每通道控制位，从源操作数的每个通道的相应部分中选择数据元素的集合。这些集合的元素被复制到目标操作数的每个通道的相应部分中的指定字段。混洗指令的另一实施例还指定第二源操作数，所有操作数具有被划分为多个数据元素的相应通道。根据每通道控制位选择的集合包含来自第一源操作数的每个通道部分的数据元素和来自第二源操作数的每个对应通道部分的数据元素。将元素复制到目标操作数的每个通道中的指定字段。

9. 发明申请

US20110307687A1 IN-LANE VECTOR SHUFFLE INSTRUCTIONS 有权
标题翻译：在线路向量小指示
公开(公告)号：US20110307687A1
公开(公告)日：2011-12-15
申请号：US13219418
申请日：2011-08-26
申请人： ZEEV SPERBER , Robert Valentine , Benny Eitan , Doron Orenstein
发明人： ZEEV SPERBER , Robert Valentine , Benny Eitan , Doron Orenstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/3885 , G06F9/3887
摘要： In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands having corresponding lanes, each lane divided into corresponding portions of multiple data elements. Sets of data elements are selected from corresponding portions of every lane of the source operand according to per-lane control bits. Elements of these sets are copied to specified fields in corresponding portions of every lane of the destination operand. Another embodiment of the shuffle instruction also specifies a second source operand, all operands having corresponding lanes divided into multiple data elements. A set selected according to per-lane control bits contains data elements from every lane portion of a first source operand and data elements from every corresponding lane portion of the second source operand. Set elements are copied to specified fields in every lane of the destination operand.
摘要翻译：描述车道内向量随机操作。在一个实施例中，混洗指令指定每通道控制位，源操作数和目的地操作数的字段，这些操作数具有相应的通道，每个通道被划分为多个数据元素的相应部分。根据每通道控制位，从源操作数的每个通道的相应部分中选择数据元素的集合。这些集合的元素被复制到目标操作数的每个通道的相应部分中的指定字段。混洗指令的另一实施例还指定第二源操作数，所有操作数具有被划分为多个数据元素的相应通道。根据每通道控制位选择的集合包含来自第一源操作数的每个通道部分的数据元素和来自第二源操作数的每个对应通道部分的数据元素。将元素复制到目标操作数的每个通道中的指定字段。

10. 发明授权

US08281109B2 Compressed instruction format 有权
标题翻译：压缩指令格式
公开(公告)号：US08281109B2
公开(公告)日：2012-10-02
申请号：US11965669
申请日：2007-12-27
申请人： Robert Valentine , Doron Orenstein , Bret Toll
发明人： Robert Valentine , Doron Orenstein , Bret Toll
IPC分类号： G06F9/45
CPC分类号： G06F9/30 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/30174 , G06F9/30178 , G06F9/30185 , G06F9/3816 , G06F9/382
摘要： A technique for decoding an instruction in a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set extensions are supported, and increased functionality is provided, without expanding the code size and, in some cases, reducing the code size.
摘要翻译：一种解码可变长度指令集中的指令的技术。在一个实施例中，描述了指令编码，其中支持遗留，现在和将来的指令集扩展，并且提供增加的功能，而不扩展代码大小，并且在一些情况下减少代码大小。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式