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1. 发明授权

US09256497B2 Checkpoints associated with an out of order architecture 有权
标题翻译：与乱序架构相关联的检查点
公开(公告)号：US09256497B2
公开(公告)日：2016-02-09
申请号：US14224233
申请日：2014-03-25
申请人： Denis M. Khartikov , John H. Kelm , Naveen Neelakantam
发明人： Denis M. Khartikov , John H. Kelm , Naveen Neelakantam
IPC分类号： G06F11/00 , G06F11/14 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3859 , G06F9/3863 , G06F11/1407
摘要： A checkpoint technique associated with an out of order based architecture of a processing device is described. An instruction may be received by its retirement unit and an identification as to whether the instruction is associated with a speculative error is performed. If the instruction is associated with the speculative error, then a first operation may be performed to replace state values of a first checkpoint of the processing device with state values of a second checkpoint. If the instruction is not associated with the speculative error, then the second checkpoint state may be updated based on the instruction.
摘要翻译：描述了与处理设备的基于无序的架构相关联的检查点技术。其退出单元可以接收指令，并且执行关于指令是否与推测性错误相关联的标识。如果指令与推测性错误相关联，则可以执行第一操作以用第二检查点的状态值替换处理设备的第一检查点的状态值。如果该指令不与推测性错误相关联，则可以基于指令更新第二检查点状态。

2. 发明申请

US20150278097A1 Instruction and Logic for Reducing Data Cache Evictions in an Out-Of-Order Processor 有权
标题翻译：用于减少无序处理器中的数据缓存驱逐的指令和逻辑
公开(公告)号：US20150278097A1
公开(公告)日：2015-10-01
申请号：US14228697
申请日：2014-03-28
申请人： John H. Kelm , Demos Pavlou , Mirem Hyuseinova
发明人： John H. Kelm , Demos Pavlou , Mirem Hyuseinova
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F8/52 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3859 , G06F12/0804 , G06F12/0811 , G06F12/12 , G06F2212/1016 , G06F2212/621
摘要： A processor includes a resource scheduler, a dispatcher, and a memory execution unit. The memory execution unit includes logic to identify an executed, unretired store operation in a memory ordered buffer, determine that the store operation is speculative, determine whether an associated cache line in a data cache is non-speculative, and determine whether to block a write of the store operation results to the data cache based upon the determination that the store operation is speculative and a determination that the associated cache line is non-speculative.
摘要翻译：处理器包括资源调度器，调度器和存储器执行单元。存储器执行单元包括用于识别在存储器有序缓冲器中执行的未被存储的存储操作的逻辑，确定存储操作是推测性的，确定数据高速缓存中的相关联的高速缓存行是否是不推测的，并且确定是否阻止写基于确定存储操作是推测性的确定和相关联的高速缓存行是非投机性的确定，将存储操作结果发送到数据高速缓存。

3. 发明授权

US09471292B2 Binary translation reuse in a system with address space layout randomization 有权
标题翻译：具有地址空间布局随机化的系统中的二进制翻译重用
公开(公告)号：US09471292B2
公开(公告)日：2016-10-18
申请号：US14256044
申请日：2014-04-18
申请人： David N. Mackintosh , John H. Kelm , Neil A. Campbell
发明人： David N. Mackintosh , John H. Kelm , Neil A. Campbell
IPC分类号： G06F9/45 , G06F12/10
CPC分类号： G06F8/52 , G06F12/0223 , G06F12/1009 , G06F12/1027 , G06F21/54 , G06F2212/1016
摘要： Generally, this disclosure provides systems, methods and computer readable media for binary translation (BT) reuse. The system may include a (BT) module to translate a region of code from a first instruction set architecture (ISA) to a second ISA, for execution associated with a first process. The BT module may also be configured to store a first physical page number associated with the translated code and the first process. The system may also include a processor to execute the translated code and to update a virtual address instruction pointer associated with the execution. The system may further include a translation reuse module to validate the translated code for reuse by a second process. The validation may include generating a second physical page number based on a page table mapping of the updated virtual address instruction pointer and matching the second physical page number to the stored first physical page number.
摘要翻译：通常，本公开提供用于二进制翻译（BT）重用的系统，方法和计算机可读介质。该系统可以包括用于将代码区域从第一指令集架构（ISA）转换到第二ISA的（BT）模块，用于与第一进程相关联的执行。 BT模块还可以被配置为存储与翻译的代码和第一进程相关联的第一物理页码。该系统还可以包括执行转换代码并更新与执行相关联的虚拟地址指令指针的处理器。该系统还可以包括翻译重用模块，以验证翻译的代码以供第二过程重用。验证可以包括基于更新的虚拟地址指令指针的页表映射并将第二物理页号与所存储的第一物理页号进行匹配来生成第二物理页号。

4. 发明申请

US20150301841A1 BINARY TRANSLATION REUSE IN A SYSTEM WITH ADDRESS SPACE LAYOUT RANDOMIZATION 有权
标题翻译：在具有地址空间布局约束的系统中的二进制翻译重用
公开(公告)号：US20150301841A1
公开(公告)日：2015-10-22
申请号：US14256044
申请日：2014-04-18
申请人： DAVID N. MACKINTOSH , JOHN H. KELM , NEIL A. CAMPBELL
发明人： DAVID N. MACKINTOSH , JOHN H. KELM , NEIL A. CAMPBELL
IPC分类号： G06F9/455
CPC分类号： G06F8/52 , G06F12/0223 , G06F12/1009 , G06F12/1027 , G06F21/54 , G06F2212/1016
摘要： Generally, this disclosure provides systems, methods and computer readable media for binary translation (BT) reuse. The system may include a (BT) module to translate a region of code from a first instruction set architecture (ISA) to a second ISA, for execution associated with a first process. The BT module may also be configured to store a first physical page number associated with the translated code and the first process. The system may also include a processor to execute the translated code and to update a virtual address instruction pointer associated with the execution. The system may further include a translation reuse module to validate the translated code for reuse by a second process. The validation may include generating a second physical page number based on a page table mapping of the updated virtual address instruction pointer and matching the second physical page number to the stored first physical page number.
摘要翻译：通常，本公开提供用于二进制翻译（BT）重用的系统，方法和计算机可读介质。该系统可以包括用于将代码区域从第一指令集架构（ISA）转换到第二ISA的（BT）模块，用于与第一进程相关联的执行。 BT模块还可以被配置为存储与翻译的代码和第一进程相关联的第一物理页码。该系统还可以包括执行转换代码并更新与执行相关联的虚拟地址指令指针的处理器。该系统还可以包括翻译重用模块，以验证翻译的代码以供第二过程重用。验证可以包括基于更新的虚拟地址指令指针的页表映射并将第二物理页号与所存储的第一物理页号进行匹配来生成第二物理页号。

5. 发明申请

US20150277975A1 Instruction and Logic for a Memory Ordering Buffer 有权
标题翻译：内存订购缓冲区的指令和逻辑
公开(公告)号：US20150277975A1
公开(公告)日：2015-10-01
申请号：US14229007
申请日：2014-03-28
申请人： John H. Kelm , Denis M. Khartikov , Naveen Neelakantam
发明人： John H. Kelm , Denis M. Khartikov , Naveen Neelakantam
IPC分类号： G06F9/48 , G06F9/30 , G06F12/08
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30174 , G06F9/3808 , G06F9/3822 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： A processor includes an allocator with logic assigning alias hardware resources to instructions within an atomic region of instructions. The atomic region includes reordered instructions. The processor also includes a dispatcher with logic to dispatch instructions from the atomic region of instructions for execution. Furthermore, the processor includes a memory execution unit with logic to populate the memory execution unit with the instructions from the atomic region of instructions including reordered instructions, receive snoop requests and determine whether the snoop request matches memory address data of elements within the memory execution unit, and prevent reassignment of alias hardware resources for any load instructions that are eligible to match the snoop requests.
摘要翻译：处理器包括具有向指令的原子区域内的指令分配别名硬件资源的逻辑的分配器。原子区域包括重新排序的指令。该处理器还包括一个调度器，该调度器具有从用于执行的指令的原子区域分派指令的逻辑。此外，处理器包括具有逻辑的存储器执行单元，该逻辑使用来自包括重新排序的指令，接收窥探请求的指令的原子区域的指令来填充存储器执行单元，并且确定窥探请求是否匹配存储器执行单元内的元素的存储器地址数据，并且防止别名硬件资源重新分配给符合snoop请求的任何加载指令。

6. 发明授权

US09569212B2 Instruction and logic for a memory ordering buffer 有权
标题翻译：存储器排序缓冲区的指令和逻辑
公开(公告)号：US09569212B2
公开(公告)日：2017-02-14
申请号：US14229007
申请日：2014-03-28
申请人： John H. Kelm , Denis M. Khartikov , Naveen Neelakantam
发明人： John H. Kelm , Denis M. Khartikov , Naveen Neelakantam
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30174 , G06F9/3808 , G06F9/3822 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： A processor includes an allocator with logic assigning alias hardware resources to instructions within an atomic region of instructions. The atomic region includes reordered instructions. The processor also includes a dispatcher with logic to dispatch instructions from the atomic region of instructions for execution. Furthermore, the processor includes a memory execution unit with logic to populate the memory execution unit with the instructions from the atomic region of instructions including reordered instructions, receive snoop requests and determine whether the snoop request matches memory address data of elements within the memory execution unit, and prevent reassignment of alias hardware resources for any load instructions that are eligible to match the snoop requests.
摘要翻译：处理器包括具有向指令的原子区域内的指令分配别名硬件资源的逻辑分配器。原子区域包括重新排序的指令。该处理器还包括一个调度器，该调度器具有从用于执行的指令的原子区域分派指令的逻辑。此外，处理器包括具有逻辑的存储器执行单元，该逻辑使用来自包括重新排序的指令，接收窥探请求的指令的原子区域的指令来填充存储器执行单元，并且确定窥探请求是否匹配存储器执行单元内的元素的存储器地址数据，并且防止别名硬件资源重新分配给符合snoop请求的任何加载指令。

7. 发明申请

US20150277914A1 LOCK ELISION WITH BINARY TRANSLATION BASED PROCESSORS 审中-公开
标题翻译：基于二进制翻译的处理器的锁定
公开(公告)号：US20150277914A1
公开(公告)日：2015-10-01
申请号：US14227014
申请日：2014-03-27
申请人： John H. Kelm , Naveen Neelakantam , Denis M. Khartikov
发明人： John H. Kelm , Naveen Neelakantam , Denis M. Khartikov
IPC分类号： G06F9/30
CPC分类号： G06F9/30087 , G06F9/45516 , G06F9/4552
摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for detection and exploitation of lock elision opportunities with binary translation based processors. The device may include a dynamic binary translation (DBT) module to translate a region of code from a first instruction set architecture (ISA) to translated code in a second ISA and to detect and elide a lock associated with a critical section of the region of code. The device may also include a processor to speculatively execute the translated code in the critical section. The device may further include a transactional support processor to detect a memory access conflict associated with the lock and/or critical section during the speculative execution, roll back the speculative execution in response to the detection, and commit the speculative execution in the absence of the detection.
摘要翻译：通常，本公开提供了用于基于二进制翻译的处理器来检测和利用锁定机会的系统，设备，方法和计算机可读介质。该设备可以包括动态二进制转换（DBT）模块，以将来自第一指令集体系结构（ISA）的代码区域转换为第二ISA中的转换代码，并且检测和删除与该区域的关键部分相关联的锁定码。该设备还可以包括在临界区域中推测性地执行转换的代码的处理器。该装置还可以包括事务支持处理器，用于在推测性执行期间检测与锁和/或关键部分相关联的存储器访问冲突，以响应于该检测来回滚推测性执行，并且在没有检测。

8. 发明申请

US20150278025A1 CHECKPOINTS ASSOCIATED WITH AN OUT OF ORDER ARCHITECTURE 有权
标题翻译：与订单结构相关的检查点
公开(公告)号：US20150278025A1
公开(公告)日：2015-10-01
申请号：US14224233
申请日：2014-03-25
申请人： Dennis M. Khartikov , John H. Kelm , Naveen Neelakantam
发明人： Dennis M. Khartikov , John H. Kelm , Naveen Neelakantam
IPC分类号： G06F11/14 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3859 , G06F9/3863 , G06F11/1407
摘要： A checkpoint technique associated with an out of order based architecture of a processing device is described. An instruction may be received by its retirement unit and an identification as to whether the instruction is associated with a speculative error is performed. If the instruction is associated with the speculative error, then a first operation may be performed to replace state values of a first checkpoint of the processing device with state values of a second checkpoint. If the instruction is not associated with the speculative error, then the second checkpoint state may be updated based on the instruction.
摘要翻译：描述了与处理设备的基于无序的架构相关联的检查点技术。其退出单元可以接收指令，并且执行关于指令是否与推测性错误相关联的标识。如果指令与推测性错误相关联，则可以执行第一操作以用第二检查点的状态值替换处理设备的第一检查点的状态值。如果该指令不与推测性错误相关联，则可以基于指令更新第二检查点状态。

9. 发明申请

US20150277915A1 Instruction and Logic for Support of Code Modification 有权
标题翻译：支持代码修改的指令和逻辑
公开(公告)号：US20150277915A1
公开(公告)日：2015-10-01
申请号：US14229161
申请日：2014-03-28
申请人： John H. Kelm , David P. Keppel , David N. Mackintosh
发明人： John H. Kelm , David P. Keppel , David N. Mackintosh
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30174 , G06F9/4552 , G06F12/0875 , G06F2212/452
摘要： A processor includes support for executing binary-translated code including code modifications. The processor includes a processor core that includes a cache to store translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected. The processor core also includes logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor core further includes logic to set a translation indicator in the cache corresponding to the memory location to indicate that it includes translated code to be protected. The processor core also includes logic to request senior store buffer drains of other processor cores of the processor based upon the execution of the translated instruction.
摘要翻译：处理器包括执行包括代码修改的二进制翻译代码的支持。处理器包括处理器核心，其包括用于存储来自物理图的转换指示符的高速缓存，每个转换指示符，以指示对应的存储器位置是否包括要保护的转换代码。处理器核还包括执行翻译指令的逻辑。转换后的指令从存储在存储单元中的指令转换。处理器核心还包括用于设置与存储器位置相对应的高速缓存中的转换指示符以指示其包括要保护的转换代码的逻辑。处理器核心还包括基于转换的指令的执行来请求处理器的其他处理器核心的高级存储缓冲器排水的逻辑。

10. 发明授权

US09652268B2 Instruction and logic for support of code modification 有权
公开(公告)号：US09652268B2
公开(公告)日：2017-05-16
申请号：US14229161
申请日：2014-03-28
申请人： John H. Kelm , David P. Keppel , David N. Mackintosh
发明人： John H. Kelm , David P. Keppel , David N. Mackintosh
IPC分类号： G06F9/00 , G06F9/44 , G06F9/455
CPC分类号： G06F9/30174 , G06F9/4552 , G06F12/0875 , G06F2212/452
摘要： A processor includes support for executing binary-translated code including code modifications. The processor includes a processor core that includes a cache to store translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected. The processor core also includes logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor core further includes logic to set a translation indicator in the cache corresponding to the memory location to indicate that it includes translated code to be protected. The processor core also includes logic to request senior store buffer drains of other processor cores of the processor based upon the execution of the translated instruction.

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