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21. 发明申请

US20030135531A1 Microprocessor floating point divider 失效
标题翻译：微处理器浮点分频器
公开(公告)号：US20030135531A1
公开(公告)日：2003-07-17
申请号：US10036116
申请日：2001-12-26
发明人： Andrew J. Beaumont-Smith , Sridhar Samudrala
IPC分类号： G06F007/52
CPC分类号： G06F7/535 , G06F7/4873 , G06F7/49936 , G06F7/5375
摘要： The specification discloses a structure of and a method of operating a subtractive division (SD) cell where a portion of the partial remainder or estimated partial remainder directly indicates the next quotient digit. More particularly, by sufficiently constraining the prescaled range for each possible divisor, only a few bits of the partial remainder (the exact number dependent upon the radix), along with their related carries (if any), directly indicate the value of the next quotient digit. Because fewer bits of the partial remainder are needed to make this determination than needed in related art devices, and further because no look-up table or hard-coded decision tree is required, calculation time within each SD cell is shorter than related art devices. Having a shorter calculation time within each SD cell allows for either completion of a greater number of SD cells within each clock cycle, or completion of the calculation to full precision in less time.
摘要翻译：本说明书公开了一种操作减法（SD）单元的结构和方法，其中部分余数或估计的部分余数的一部分直接指示下一个商数。更具体地说，通过充分约束每个可能的除数的预定范围，只有部分余数的几个位（取决于基数的确切数字）及其相关的运算（如果有的话）直接指示下一个商的值数字。因为需要部分余数的比特少于相关技术装置中所需的这种确定，而且由于不需要查找表或硬编码决策树，所以每个SD小区内的计算时间比现有技术的装置短。在每个SD单元内具有更短的计算时间允许在每个时钟周期内完成更多数量的SD单元，或者在更短的时间内完成计算以达到全精度。

22. 发明申请

US20020178198A1 Comparator unit for comparing values of floating point operands 有权
标题翻译：用于比较浮点运算数值的比较器单元
公开(公告)号：US20020178198A1
公开(公告)日：2002-11-28
申请号：US10035586
申请日：2001-12-28
申请人： Sun Microsystems, Inc.
发明人： Guy L. Steele JR.
IPC分类号： G06F007/38
CPC分类号： G06F5/012 , G06F5/015 , G06F7/026 , G06F7/483 , G06F7/4873 , G06F7/4876 , G06F7/49905 , G06F9/30014 , G06F9/30021 , G06F9/30094 , G06F9/3861 , G06F9/3885
摘要： A floating point comparator circuit for comparing a plurality of floating point operands includes a plurality of analysis circuits, one for each of the floating point operands, configured to determine a format of each of the floating point operands based upon floating point status information encoded within each of the floating point operands, and a result generator circuit coupled to the analysis circuits, the result generator circuit configured to generate a result signal based on the format determined by each analysis circuit and based on a comparative relationship among the floating point operands. The format of each of the floating point operands may be from a group comprising: not-a-number (NaN), infinity, normalized, denormalized, zero, invalid operation, overflow, underflow, division by zero, exact, and inexact. The result generator circuit may ignore the encoded floating point statuses of the plurality of floating point operands when comparing just the magnitudes of the plurality of floating point operands.
摘要翻译：用于比较多个浮点操作数的浮点比较器电路包括多个分析电路，每个分析电路用于每个浮点操作数，其被配置为基于在每个浮点操作数中编码的浮点状态信息来确定每个浮点操作数的格式以及耦合到分析电路的结果生成器电路，所述结果生成器电路被配置为基于由每个分析电路确定的格式并且基于所述浮点操作数之间的比较关系生成结果信号。每个浮点操作数的格式可以来自包括以下的组：非数字（NaN），无穷大，归一化，非归一化，零，无效操作，溢出，下溢，除以零，精确和不精确。当仅比较多个浮点操作数的大小时，结果生成器电路可以忽略多个浮点操作数的编码的浮点状态。

23. 发明授权

US06384748B1 Method of encoding numeric data and manipulating the same 失效
标题翻译：编码数字数据并进行操作的方法
公开(公告)号：US06384748B1
公开(公告)日：2002-05-07
申请号：US09434693
申请日：1999-11-05
申请人： Steven Asherman , Arun Kumar
发明人： Steven Asherman , Arun Kumar
IPC分类号： H03M700
CPC分类号： G06F7/38 , G06F7/485 , G06F7/4873 , G06F7/4876 , H03M7/24
摘要： Numeric data is encoded as a variable-length, NULL-terminated string. The first character of the string represents the sign of the numeric data, the second character of the string represents the exponent of the numeric data, the following characters represent the digits of the mantissa of the numeric data and the final character is a termination character.
摘要翻译：数字数据被编码为可变长度，以NULL结尾的字符串。字符串的第一个字符表示数字数据的符号，字符串的第二个字符表示数字数据的指数，以下字符表示数字数据的尾数的数字，最后一个字符是终止字符。

24. 发明授权

US06351760B1 Division unit in a processor using a piece-wise quadratic approximation technique 有权
标题翻译：使用分段二次逼近技术的处理器中的分割单元
公开(公告)号：US06351760B1
公开(公告)日：2002-02-26
申请号：US09240312
申请日：1999-01-29
申请人： Ravi Shankar , Subramania I. Sudharsanan
发明人： Ravi Shankar , Subramania I. Sudharsanan
IPC分类号： G06F752
CPC分类号： G06F7/535 , G06F7/4873 , G06F7/49947 , G06F7/49957 , G06F7/49963 , G06F9/30014 , G06F2207/3884
摘要： A computation unit computes a division operation Y/X by determining the value of a divisor reciprocal 1/X and multiplying the reciprocal by a numerator Y. The reciprocal 1/X value is determined using a quadratic approximation having a form: Ax2+Bx+C, where coefficients A, B, and C are constants that are stored in a storage or memory such as a read-only memory (ROM). The bit length of the coefficients determines the error in a final result. Storage size is reduced through use of “least mean square error”techniques in the determination of the coefficients that are stored in the coefficient storage. During the generation of partial products x2, Ax2, and Bx, the process of rounding is eliminated, thereby reducing the computational logic to implement the division functionality.
摘要翻译：计算单元通过确定除数互逆1 / X的值并将倒数乘以分子Y来计算除法运算Y / X。使用具有以下形式的二次近似来确定倒数1 / X值：其中系数A， B和C是存储在诸如只读存储器（ROM）的存储器或存储器中的常数。系数的位长决定了最终结果中的误差。在确定系数存储器中存储的系数时，通过使用“最小均方误差”技术来减少存储大小。在部分产品x2，Ax2和Bx的生成期间，舍入的过程被消除，从而减少了实现分割功能的计算逻辑。

25. 发明授权

US5710730A Divide to integer 失效
标题翻译：划分为整数
公开(公告)号：US5710730A
公开(公告)日：1998-01-20
申请号：US414255
申请日：1995-03-31
申请人： Ronald Morton Smith, Sr.
发明人： Ronald Morton Smith, Sr.
IPC分类号： G06F7/499 , G06F7/52 , G06F7/535 , G06F7/38
CPC分类号： G06F7/535 , G06F7/4873 , G06F7/49957 , G06F7/49978
摘要： A system and method for providing an interruptible remainder instruction that can produce a quotient as well as a remainder. Remainders are computed through an iterative procedure. This procedure is carried out in a computer system's hardware by following a series of steps, the series being interruptible at any point. Each step reduces the magnitude of the dividend until the final remainder can be obtained. In the intermediate steps, the sign of the new (smaller in magnitude) dividend is kept the same as the sign of the original dividend, and the value Ni (which can be considered part of the quotient) is rounded toward zero. Only in the last step must the sign of the operands be considered and directed rounding be performed. Throughout the remainder operation, the partial quotients can be saved so that upon completion, not only has the remainder been computed, but so has the quotient.
摘要翻译：一种用于提供可产生商以及余数的可中断余数指令的系统和方法。剩余值通过迭代过程计算。该过程通过以下一系列步骤在计算机系统的硬件中进行，该系列在任何时候都是可中断的。每个步骤减少分红的幅度，直到可以获得最后的余数。在中间步骤中，新（较小幅度）的股息的符号与原始股利的符号保持一致，并且值Ni（可以被认为是商的一部分）被舍入为零。只有在最后一步必须考虑操作数的符号并执行四舍五入。在剩余操作中，可以保存部分商，以便在完成后，不仅计算余数，而且商数也是如此。

26. 发明授权

US5633818A Method and apparatus for performing floating point arithmetic operation and rounding the result thereof 失效
标题翻译：用于进行浮点算术运算并舍入其结果的方法和装置
公开(公告)号：US5633818A
公开(公告)日：1997-05-27
申请号：US438142
申请日：1995-05-08
申请人： Takashi Taniguchi
发明人： Takashi Taniguchi
IPC分类号： G06F7/02 , G06F7/483 , G06F7/499 , G06F7/52 , G06F7/53 , G06F7/533 , G06F7/535 , G06F7/544 , G06F7/552 , G06F17/17 , G06F7/38 , G06F7/00
CPC分类号： G06F7/535 , G06F7/026 , G06F7/544 , G06F7/5525 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49952 , G06F7/49957
摘要： An apparatus uses a sticky digit in rounding an interim solution Yr into a final approximate solution Ye for an infinite precise solution Y, determined by a function F according to Y=F(X) with respect to digital data X. The apparatus includes a partial product generator receiving a multiplicand and a multiplier, at least one of which represents an interim solution Yr, for generating a plurality of partial products; a sign inversion generator for generating a sign inversion value, expressed in the same format as the partial products, from at least a lower part of a subtrahend to enable place matching, where the subtrahend represents the digital data X; an adder for adding the partial products and the sign inversion value; a detector which, in response to the addition result, detects whether the subtrahend or a product of the multiplicand and multiplier is greater; and a sticky digit generator for generating the sticky digit in response to the detection result.
摘要翻译：一个装置使用一个粘性数字将一个临时解决方案Yr舍入到最终的近似解中，对于无限精确解Y，由相对于数字数据X的Y = F（X）的函数F确定。该装置包括部分产品生成器接收被乘数和乘数，其中至少一个表示临时解Yr，用于生成多个部分乘积; 符号反转生成器，用于从减数的至少下部生成与所述部分乘积相同格式表示的符号反转值，以使得能够进行位置匹配，其中所述减法表示所述数字数据X; 加法器，用于添加部分乘积和符号反转值; 检测器，响应于相加结果，检测所述被乘数和乘法器的乘法或乘积是否较大; 以及用于响应于检测结果产生粘性数字的粘性数字发生器。

27. 发明授权

US5563818A Method and system for performing floating-point division using selected approximation values 失效
标题翻译：使用选择的近似值执行浮点除法的方法和系统
公开(公告)号：US5563818A
公开(公告)日：1996-10-08
申请号：US354402
申请日：1994-12-12
申请人： Ramesh C. Agarwal , Andrew A. Bjorksten , Freg G. Gustavson
发明人： Ramesh C. Agarwal , Andrew A. Bjorksten , Freg G. Gustavson
IPC分类号： G06F1/035 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F1/0356 , G06F2101/12 , G06F2207/5352 , G06F2207/5354 , G06F2207/5356 , G06F7/4873 , G06F7/49963
摘要： A method and system for performing floating-point division of a dividend by a divisor within a floating-point unit having multiply and add functions are disclosed. In performing floating-point division, a quotient having a mantissa is produced. The method uses an approximation based on a linear approximation stored within a first table. The first approximation approximates two divided by the divisor. A second table value is also selected from the table lookup. The second table value approximates the reciprocal of the divisor squared. Both the first and second table values operate as linear correction terms. Also according to the present invention, a method and system are disclosed that perform an early exit check during the division operation to confirm whether the resultant quotient has an acceptable accuracy and if the accuracy is unacceptable, then perform a rounding correction based upon a given rounding boundary.
摘要翻译：公开了一种用于在具有乘法和加法函数的浮点单元中由除数进行除数的浮点除法的方法和系统。在执行浮点除法时，产生具有尾数的商。该方法使用基于存储在第一表内的线性近似的近似。第一个近似值近似于除数除数的二分之一。还从表查找中选择第二个表值。第二个表格值近似于除数平方的倒数。第一和第二表值都作为线性校正项操作。同样根据本发明，公开了一种方法和系统，其在分割操作期间执行早期退出检查以确认所得到的商是否具有可接受的准确性，并且如果精度是不可接受的，则基于给定舍入执行舍入校正边界。

28. 发明授权

US5515308A Floating point arithmetic unit using modified Newton-Raphson technique for division and square root 失效
标题翻译：使用改进的牛顿 - 拉夫逊技术进行划分和平方根的浮点运算单元
公开(公告)号：US5515308A
公开(公告)日：1996-05-07
申请号：US524966
申请日：1995-09-08
申请人： Alan H. Karp , Peter Markstein , Dennis Brzezinski
发明人： Alan H. Karp , Peter Markstein , Dennis Brzezinski
IPC分类号： G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/552 , G06F7/38
CPC分类号： G06F7/535 , G06F7/5525 , G06F2207/382 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49936 , G06F7/49957
摘要： A floating point processing system which uses a multiplier unit and an adder unit to perform floating point division and square root operations using both a conventional and a modified form of the Newton-Raphson method. The modified form of the Newton-Raphson method is used in place of the final iteration of the conventional Newton-Raphson so as to compute high precision approximated results with a substantial improvement in speed. The invention computes approximated results faster and simplifies hardware requirements because no multiplications of numbers of the precision of the result are required.
摘要翻译：一种浮点处理系统，其使用乘法器单元和加法器单元来使用牛顿 - 拉夫逊方法的常规和修改形式来执行浮点除法和平方根操作。使用Newton-Raphson方法的修改形式来代替常规牛顿 - 拉夫森的最终迭代，以便计算出高精度近似结果，具有显着的速度提高。本发明更快地计算近似结果并简化硬件要求，因为不需要对结果的精度数进行乘法运算。

29. 发明授权

US5404324A Methods and apparatus for performing division and square root computations in a computer 失效
标题翻译：在计算机中执行划分和平方根计算的方法和装置
公开(公告)号：US5404324A
公开(公告)日：1995-04-04
申请号：US146895
申请日：1993-11-01
申请人： Glenn T. Colon-Bonet
发明人： Glenn T. Colon-Bonet
IPC分类号： G06F7/38 , G06F7/483 , G06F7/52 , G06F7/535 , G06F7/537 , G06F7/552
CPC分类号： G06F7/535 , G06F7/5375 , G06F7/5525 , G06F2207/5528 , G06F7/4873 , G06F7/49957
摘要： An apparatus for performing floating-point division and square root computations according to an IEEE rounding standard includes input data alignment circuitry, core iteration circuitry, remainder compare circuitry, and round and select circuitry. The core iteration circuitry includes digit selector circuitry; remainder registers; quotient logic circuitry; remainder formation circuitry; and quotient registers for storing the quotient Q, incremented quotient Q+1, and decremented quotient Q-1. The remainder formation circuitry produces sum and carry bits of the P.sub.j+1 term, which are in turn fed back to the partial remainder registers and used in subsequent iterations. The quotient logic circuitry builds the quotient Q and maintains the respective quotient Q, Q+1, Q-1 registers. The outputs of these registers are fed back to the quotient logic circuitry for use in subsequent iterations. The remainder compare circuitry comprises a remainder comparator and a logic circuit. The remainder comparator receives the sum and carry bits for the P.sub.j+1 terms and outputs the "Sign" and "Zero" bits. These bits are received by the logic circuit along with a rounding mode signal, which is indicative of the selected rounding mode, e.g., shifted or normalized round to nearest, round to zero, or round to infinity. The logic circuit outputs a round select signal that selects a quotient select signal for selecting, as the final rounded quotient, the output of one of the quotient registers Q, Q+1, or Q-1. The round and select circuitry includes a round block for positive remainders and a round block for negative remainders.
摘要翻译：用于根据IEEE舍入标准执行浮点分割和平方根计算的装置包括输入数据对准电路，核心迭代电路，余数比较电路以及循环和选择电路。核心迭代电路包括数字选择器电路; 余数寄存器; 商逻辑电路; 余数形成电路; 以及用于存储商Q，递增商Q + 1和递减商Q-1的商寄存器。剩余形成电路产生Pj + 1项的和和进位位，这些位又反馈到部分余数寄存器并用于后续迭代。商逻辑电路构建商Q并维持相应的商Q，Q + 1，Q-1寄存器。这些寄存器的输出反馈到商逻辑电路，用于后续迭代。剩余比较电路包括余数比较器和逻辑电路。剩余比较器接收和并携带Pj + 1项的位，并输出“符号”和“零”位。这些位由逻辑电路连同舍入模式信号一起被接收，舍入模式信号指示所选择的舍入模式，例如，移位或归一化到最接近，最近到零，或者到达到无穷大。逻辑电路输出一个圆选择信号，其选择商选择信号，用于选择商寄存器Q，Q + 1或Q-1之一的输出作为最终舍入商。圆形和选择电路包括用于正残余物的圆形块和用于负余留物的圆形块。

30. 发明授权

US4979142A Two-bit floating point divide circuit with single carry-save adder 失效
标题翻译：具有单进位保存加法器的两位浮点除法电路
公开(公告)号：US4979142A
公开(公告)日：1990-12-18
申请号：US339261
申请日：1989-04-17
申请人： Richard G. Allen , Donald L. Freerksen
发明人： Richard G. Allen , Donald L. Freerksen
IPC分类号： G06F7/537 , G06F7/483 , G06F7/506 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F2207/5352 , G06F7/4873
摘要： Apparatus and method for performing floating point divide operations in 2-bit, non-restoring iterations, wherein multiples of the divisor are formed by selective gating of one or more representations of the divisor into a single 3-input adder circuit, to calculate the partial quotients and subsequent partial dividends. The apparatus produces, without the need of separate holding registers, the zero, 1/2, 3/4, 1 and 3/2 multiples of the divisor.

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