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1. 发明授权

US5563818A Method and system for performing floating-point division using selected approximation values 失效
标题翻译：使用选择的近似值执行浮点除法的方法和系统
公开(公告)号：US5563818A
公开(公告)日：1996-10-08
申请号：US354402
申请日：1994-12-12
申请人： Ramesh C. Agarwal , Andrew A. Bjorksten , Freg G. Gustavson
发明人： Ramesh C. Agarwal , Andrew A. Bjorksten , Freg G. Gustavson
IPC分类号： G06F1/035 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F1/0356 , G06F2101/12 , G06F2207/5352 , G06F2207/5354 , G06F2207/5356 , G06F7/4873 , G06F7/49963
摘要： A method and system for performing floating-point division of a dividend by a divisor within a floating-point unit having multiply and add functions are disclosed. In performing floating-point division, a quotient having a mantissa is produced. The method uses an approximation based on a linear approximation stored within a first table. The first approximation approximates two divided by the divisor. A second table value is also selected from the table lookup. The second table value approximates the reciprocal of the divisor squared. Both the first and second table values operate as linear correction terms. Also according to the present invention, a method and system are disclosed that perform an early exit check during the division operation to confirm whether the resultant quotient has an acceptable accuracy and if the accuracy is unacceptable, then perform a rounding correction based upon a given rounding boundary.
摘要翻译：公开了一种用于在具有乘法和加法函数的浮点单元中由除数进行除数的浮点除法的方法和系统。在执行浮点除法时，产生具有尾数的商。该方法使用基于存储在第一表内的线性近似的近似。第一个近似值近似于除数除数的二分之一。还从表查找中选择第二个表值。第二个表格值近似于除数平方的倒数。第一和第二表值都作为线性校正项操作。同样根据本发明，公开了一种方法和系统，其在分割操作期间执行早期退出检查以确认所得到的商是否具有可接受的准确性，并且如果精度是不可接受的，则基于给定舍入执行舍入校正边界。

2. 发明授权

US08099729B2 Method and device for creating and using pre-internalized program files 有权
标题翻译：用于创建和使用预内部化程序文件的方法和设备
公开(公告)号：US08099729B2
公开(公告)日：2012-01-17
申请号：US11422230
申请日：2006-06-05
申请人： Iris M. Plaxton , Samuel J. Rauch , John H. Osman , Andrew A. Bjorksten , Jason M. Bennett
发明人： Iris M. Plaxton , Samuel J. Rauch , John H. Osman , Andrew A. Bjorksten , Jason M. Bennett
IPC分类号： G06F9/455 , G06F9/45
CPC分类号： G06F9/44557 , G06F9/445 , G06F9/45504
摘要： A device (45) receives new program files (46) and uses pre-internalized images to avoid having to internalize a program file every time that program execution occurs. In one embodiment, a software Virtual Machine (50) in the device functions to implement the pre-internalization. Once the program files are pre-internalized to create images that are stored in a permanent memory (56) of the device, the images may subsequently be executed without having to perform a pre-internalization operation. Additionally, use of dynamic memory (52) is reduced in connection with subsequent program execution and execution time of new program files is reduced.
摘要翻译：设备（45）接收新的程序文件（46）并且使用预内部化的图像，以避免在每次执行程序时都必须内部化程序文件。在一个实施例中，设备中的软件虚拟机（50）用于实现预内部化。一旦程序文件被预内部化以创建存储在设备的永久存储器（56）中的图像，则可以随后执行图像而不必执行预内部化操作。此外，与随后的程序执行相关联地减少动态存储器（52）的使用，并且减少了新程序文件的执行时间。

3. 发明授权

US5930148A Method and system for verifying a digital circuit design including dynamic circuit cells that utilize diverse circuit techniques 失效
标题翻译：用于验证数字电路设计的方法和系统，包括利用多种电路技术的动态电路单元
公开(公告)号：US5930148A
公开(公告)日：1999-07-27
申请号：US767407
申请日：1996-12-16
申请人： Andrew A. Bjorksten , Brian A. Zoric , Martin S. Schmookler
发明人： Andrew A. Bjorksten , Brian A. Zoric , Martin S. Schmookler
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5031
摘要： A method and system are described, which utilize timing analysis to verify a digital circuit design that includes a plurality of dynamic logic circuit cells employing diverse circuit techniques and that may also include static logic circuit cells. For each dynamic circuit cell, a set of timing constraints is defined based upon the circuit technique employed by the associated dynamic logic circuit cell. Each timing constraint prevents a possible mode of failure of the associated dynamic logic circuit cell. The digital circuit design is then verified. The verification includes a determination of whether or not each dynamic logic circuit cell satisfies its respective set of timing constraints while connected to the other circuit cells. In an embodiment in which the digital circuit design includes a static logic circuit cell, the verification includes a verification that the static logic circuit cell has a correct inversion relationship between its input and output.
摘要翻译：描述了一种方法和系统，其利用定时分析来验证包括采用多种电路技术的多个动态逻辑电路单元并且还可以包括静态逻辑电路单元的数字电路设计。对于每个动态电路单元，基于由相关联的动态逻辑电路单元采用的电路技术来定义一组时序约束。每个时序约束阻止相关联的动态逻辑电路单元的可能的故障模式。然后验证数字电路设计。验证包括确定每个动态逻辑电路单元在连接到其它电路单元时是否满足其各自的定时约束集合。在数字电路设计包括静态逻辑电路单元的实施例中，验证包括静态逻辑电路单元在其输入和输出之间具有正确的反相关系的验证。

4. 发明授权

US5764549A Fast floating point result alignment apparatus 失效
标题翻译：快速浮点结果对齐装置
公开(公告)号：US5764549A
公开(公告)日：1998-06-09
申请号：US639573
申请日：1996-04-29
申请人： Andrew A. Bjorksten , Donald G. Mikan, Jr. , Martin S. Schmookler
发明人： Andrew A. Bjorksten , Donald G. Mikan, Jr. , Martin S. Schmookler
IPC分类号： G06F5/01
CPC分类号： G06F5/012
摘要： A device for aligning the radix point of an unaligned binary result of a floating point operation to a normalized or denormalized position is provided. The device comprises an alignment circuit that produces a shift alignment vector indicating the position of the most significant bit of the unaligned result that is set, when a normalized result is required, and that produces a shift alignment vector indicating the position of a bit of the unaligned result having the weight of a minimum allowable exponent for a given format, when a denormalized result is required. A shift register responsive to the alignment circuit shifts the unaligned result by the number of bits indicated by the shift alignment vector. The bit of the unaligned result having the weight of the minimum allowable exponent for the given format is determined by subtracting the binary value of the minimum allowable exponent from the binary value of the most significant bit of the unaligned result, wherein the difference indicates the number of bits from the most significant bit that the bit having the weight of the minimum allowable exponent is positioned.
摘要翻译：提供了用于将浮点运算的未对齐二进制结果的基数与归一化或非归一化位置对准的装置。该装置包括对准电路，当需要归一化结果时，该对准电路产生指示所设置的未对准结果的最高有效位的位置的移位对准矢量，并且产生一个移位对齐矢量，其指示位当需要非规范化结果时，对于给定格式，具有最小可允许指数权重的未对齐结果。响应于对准电路的移位寄存器将未对齐结果移位由移位对准矢量指示的位数。通过从未对齐结果的最高有效位的二进制值中减去最小可允许指数的二进制值来确定具有给定格式的最小允许指数权重的未对齐结果的位，其中该差表示数字来自最高有效位的位具有最小允许指数的权重的位被定位。

5. 发明授权

US07221188B2 Logic circuitry 有权
标题翻译：逻辑电路
公开(公告)号：US07221188B2
公开(公告)日：2007-05-22
申请号：US10967563
申请日：2004-10-18
申请人： Andrew A. Bjorksten , Khoi B. Mai , Paul C. Rossbach
发明人： Andrew A. Bjorksten , Khoi B. Mai , Paul C. Rossbach
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A logic circuit including at least one evaluate circuit coupled to a static output logic circuit. In one example, the evaluate circuit includes a dynamic node, a full keeper, an evaluate device, and a logic tree. In some examples, the output logic circuit is a sampled static output logic circuit and includes a sample device. In some examples, the logic circuit includes multiple evaluate circuits, each with a dynamic node coupled to a control gate of a transistor of the output logic circuit. Some examples may include a delay in a clock signal to increase the internal race margin.
摘要翻译：逻辑电路，包括耦合到静态输出逻辑电路的至少一个评估电路。在一个示例中，评估电路包括动态节点，完整守护者，评估设备和逻辑树。在一些示例中，输出逻辑电路是采样静态输出逻辑电路，并且包括采样器件。在一些示例中，逻辑电路包括多个评估电路，每个评估电路具有耦合到输出逻辑电路的晶体管的控制栅极的动态节点。一些示例可以包括时钟信号的延迟以增加内部游隙。

6. 发明授权

US07080373B2 Method and device for creating and using pre-internalized program files 失效
标题翻译：用于创建和使用预内部化程序文件的方法和设备
公开(公告)号：US07080373B2
公开(公告)日：2006-07-18
申请号：US09800935
申请日：2001-03-07
申请人： Iris M. Plaxton , Samuel J. Rauch , John H. Osman , Andrew A. Bjorksten , Jason M. Bennett
发明人： Iris M. Plaxton , Samuel J. Rauch , John H. Osman , Andrew A. Bjorksten , Jason M. Bennett
IPC分类号： G06F9/455 , G06F12/00
CPC分类号： G06F9/44557 , G06F9/445 , G06F9/45504
摘要： A device (45) receives new program files (46) and uses pre-internalized images to avoid having to internalize a program file every time that program execution occurs. In one embodiment, a software Virtual Machine (50) in the device functions to implement the pre-internalization. Once the program files are pre-internalized to create images that are stored in a permanent memory (56) of the device, the images may subsequently be executed without having to perform a pre-internalization operation. Additionally, use of dynamic memory (52) is reduced in connection with subsequent program execution and execution time of new program files is reduced.
摘要翻译：设备（45）接收新的程序文件（46）并且使用预内部化的图像，以避免在每次执行程序时都必须内部化程序文件。在一个实施例中，设备中的软件虚拟机（50）用于实现预内部化。一旦程序文件被预内部化以创建存储在设备的永久存储器（56）中的图像，则可以随后执行图像而不必执行预内部化操作。此外，与随后的程序执行相关联地减少动态存储器（52）的使用，并且减少了新程序文件的执行时间。

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