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1. 发明授权

US06351760B1 Division unit in a processor using a piece-wise quadratic approximation technique 有权
标题翻译：使用分段二次逼近技术的处理器中的分割单元
公开(公告)号：US06351760B1
公开(公告)日：2002-02-26
申请号：US09240312
申请日：1999-01-29
申请人： Ravi Shankar , Subramania I. Sudharsanan
发明人： Ravi Shankar , Subramania I. Sudharsanan
IPC分类号： G06F752
CPC分类号： G06F7/535 , G06F7/4873 , G06F7/49947 , G06F7/49957 , G06F7/49963 , G06F9/30014 , G06F2207/3884
摘要： A computation unit computes a division operation Y/X by determining the value of a divisor reciprocal 1/X and multiplying the reciprocal by a numerator Y. The reciprocal 1/X value is determined using a quadratic approximation having a form: Ax2+Bx+C, where coefficients A, B, and C are constants that are stored in a storage or memory such as a read-only memory (ROM). The bit length of the coefficients determines the error in a final result. Storage size is reduced through use of “least mean square error”techniques in the determination of the coefficients that are stored in the coefficient storage. During the generation of partial products x2, Ax2, and Bx, the process of rounding is eliminated, thereby reducing the computational logic to implement the division functionality.
摘要翻译：计算单元通过确定除数互逆1 / X的值并将倒数乘以分子Y来计算除法运算Y / X。使用具有以下形式的二次近似来确定倒数1 / X值：其中系数A， B和C是存储在诸如只读存储器（ROM）的存储器或存储器中的常数。系数的位长决定了最终结果中的误差。在确定系数存储器中存储的系数时，通过使用“最小均方误差”技术来减少存储大小。在部分产品x2，Ax2和Bx的生成期间，舍入的过程被消除，从而减少了实现分割功能的计算逻辑。

2. 发明授权

US06678710B1 Logarithmic number system for performing calculations in a processor 有权
标题翻译：用于在处理器中执行计算的对数编号系统
公开(公告)号：US06678710B1
公开(公告)日：2004-01-13
申请号：US09706467
申请日：2000-11-03
申请人： Ravi Shankar , Subramania I. Sudharsanan
发明人： Ravi Shankar , Subramania I. Sudharsanan
IPC分类号： G06F700
CPC分类号： G06F7/4833
摘要： A computation unit employs a logarithmic number system that uses a logarithmic numerical representation that differs from an IEEE standard representation to improve the efficiency of computation, both by reducing the time expended in performing the computation and by reducing the size of the integrated circuit that performs the computation. The illustrative computation unit employs a numerical representation that is similar to the IEEE format except that the sign term is omitted. Thus only positive numbers are represented. The value of the mantissa is defined as a fractional number between zero and one. The logarithmic number system is a useful number system domain for multiplication, division, reciprocal, square root, and power computations using multiplication, division, and square root computation techniques described by following equations: A*B=Anti-log(log(A)+log(B)), (3) A/B=Anti-log(log(A)−log(B)), (4) B½=Anti-log(log(B)/2). (5)
摘要翻译：计算单元使用对数数字系统，其使用与IEEE标准表示不同的对数数字表示，以通过减少执行计算所花费的时间和减少执行计算的集成电路的大小来提高计算效率计算。说明性计算单元采用类似于IEEE格式的数字表示，除了省略符号项。因此，仅表示正数。尾数的值被定义为零和一之间的分数。对数次数系统是使用以下等式描述的乘法，除法和平方根计算技术的乘法，除法，倒数，平方根和功率计算的有用数字系统域：

3. 发明授权

US06349319B1 Floating point square root and reciprocal square root computation unit in a processor 有权
标题翻译：处理器中的浮点平方根和倒数平方根计算单元
公开(公告)号：US06349319B1
公开(公告)日：2002-02-19
申请号：US09240765
申请日：1999-01-29
申请人： Ravi Shankar , Subramania I. Sudharsanan
发明人： Ravi Shankar , Subramania I. Sudharsanan
IPC分类号： G06F7552
CPC分类号： G06F9/30014 , G06F7/5525 , G06F2207/5521
摘要： A method of computing a square root or a reciprocal square root of a number in a computing device uses a piece-wise quadratic approximation of the number. The square root computation uses the piece-wise quadratic approximation in the form: squareroot(X)={overscore (A)}ix2+{overscore (B)}ix+{overscore (C)}i, in each interval i. The reciprocal square root computation uses the piece-wise quadratic approximation in the form: 1/squareroot(X)=Aix2+Bix+Ci, in each interval i. The coefficients {overscore (A)}i, {overscore (B)}i, and {overscore (C)}i, and Ai, Bi, and Ci are derived for the square root operation and for the reciprocal square root operation to reduce the least mean square error using a least squares approximation of a plurality of equally-spaced points within an interval. In one embodiment, 256 equally-spaced intervals are defined to represent the 23 bits of the mantissa. The coefficients are stored in a storage and accessed during execution of the square root or reciprocal square root computation instruction.
摘要翻译：在计算装置中计算数字的平方根或倒数平方根的方法使用数字的分段二次近似。平方根计算使用分段二次近似形式：在每个间隔i。互逆平方根计算使用分段二次逼近形式：在每个间隔i。导出了平方根运算和倒数平方根运算的系数{overscore（A）} i，{overscore（B）} i和{overscore（C）} i以及Ai，Bi和Ci 使用在间隔内的多个等间隔点的最小平方近似的最小均方误差。在一个实施例中，256个等间隔的间隔被定义为表示尾数的23位。系数存储在存储器中，并在执行平方根或倒数平方根计算指令期间访问。

4. 发明授权

US06341300B1 Parallel fixed point square root and reciprocal square root computation unit in a processor 有权
标题翻译：一个处理器中的平行固定点平方根和倒数平方根计算单元
公开(公告)号：US06341300B1
公开(公告)日：2002-01-22
申请号：US09240977
申请日：1999-01-29
申请人： Ravi Shankar , Subramania I. Sudharsanan
发明人： Ravi Shankar , Subramania I. Sudharsanan
IPC分类号： G06F738
CPC分类号： G06F9/30014 , G06F1/0356 , G06F7/483 , G06F7/5525 , G06F9/30036 , G06F9/30098 , G06F9/3012 , G06F9/3838 , G06F9/3853 , G06F9/3877 , G06F9/3885 , G06F2101/08 , G06F2207/3824 , G06F2207/3828 , G06F2207/5521
摘要： A parallel fixed-point square root and reciprocal square root computation uses the same coefficient tables as the floating point square root and reciprocal square root computation by converting the fixed-point numbers into a floating-point structure with a leading implicit 1. The value of a number X is stored as two fixed-point numbers. In one embodiment, the fixed-point numbers are converted to the special floating-point structure using a leading zero detector and a shifter. Following the square root computation or the reciprocal square root computation, the floating point result is shifted back into the two-entry fixed-point format. The shift count is determined by the number of leaded zeros detected during the conversion from fixed-point to floating-point format.
摘要翻译：平行定点平方根和倒数平方根计算使用与浮点平方根和倒数平方根计算相同的系数表，将固定点数转换成具有前导隐含的浮点结构。数字X被存储为两个定点数。在一个实施例中，使用前导零检测器和移位器将定点数转换为特殊浮点结构。在平方根计算或倒数平方根计算之后，浮点结果被转回到两入口定点格式。移位计数由在从定点到浮点格式的转换期间检测到的引导零的数量来确定。

5. 发明授权

US06965641B1 Apparatus and method for scalable buffering in a digital video decoder 有权
标题翻译：数字视频解码器中可扩展缓冲的装置和方法
公开(公告)号：US06965641B1
公开(公告)日：2005-11-15
申请号：US09517804
申请日：2000-03-02
申请人： Amit Gulati , Subramania I. Sudharsanan , Parthasarathy Sriram
发明人： Amit Gulati , Subramania I. Sudharsanan , Parthasarathy Sriram
IPC分类号： H04N7/12 , H04N7/26 , H04N7/50
CPC分类号： H04N19/423 , H04N19/44 , H04N19/61
摘要： A method of assigning a buffer size in a video decoder includes the step of establishing a first buffer size for a scalable buffer. A video data stream is then processed with the scalable buffer configured to the first buffer size. A second buffer size is then selected for the scalable buffer. The video stream is then processed with the scalable buffer configured to the second buffer size. Memory utilization data characterizing memory performance during processing with the scalable buffer at the first buffer size and the second buffer size is then created. Afterwards, a buffer size is assigned for the scalable buffer in accordance with the memory utilization data.
摘要翻译：在视频解码器中分配缓冲器大小的方法包括为可伸缩缓冲器建立第一缓冲器大小的步骤。然后，将视频数据流用可配置为第一缓冲区大小的可伸缩缓冲区进行处理。然后为可伸缩缓冲区选择第二个缓冲区大小。视频流然后被配置为第二缓冲器大小的可伸缩缓冲器处理。然后创建在第一缓冲区大小和第二缓冲区大小的可伸缩缓冲区的处理期间表征存储器性能的存储器利用率数据。然后，根据存储器利用数据为可伸缩缓冲器分配缓冲器大小。

6. 发明授权

US06731686B1 Apparatus and method for pipelining variable length decode and inverse quantization operations in a hybrid motion-compensated and transform coded video decoder 有权
标题翻译：用于在混合运动补偿和变换编码视频解码器中流水线化可变长度解码和逆量化操作的装置和方法
公开(公告)号：US06731686B1
公开(公告)日：2004-05-04
申请号：US09584834
申请日：2000-05-31
申请人： Subramania I. Sudharsanan , Parthasarathy Sriram , Amit Gulati
发明人： Subramania I. Sudharsanan , Parthasarathy Sriram , Amit Gulati
IPC分类号： H04B166
CPC分类号： H03M7/425 , H04N19/42 , H04N19/61 , H04N19/91
摘要： A method for pipelining variable length decode and inverse quantization operations in a hybrid motion-compensated and transform coded video decoder includes the step of mapping a new code word to a look-up table to retrieve a code word length, a zero-run length, and a quantized level. A new linear, zig-zagged position of a current coefficient is identified from the zero-run length and a previous zero-run length. The code word length is added to a current bitstream position to yield a new bitstream position. A quantization matrix coefficient from the new linear, zig-zagged position of the current coefficient is selected. The quantized level is multiplied by a predetermined value to produce a quantization product. In the case of inter block processing, a quantized level sign value is added to the quantization product. In the case of intra block processing, the quantization product does not include the quantization level sign. The quantization product is multiplied by a quantization matrix coefficient to form a derived quantization value. The derived quantization value is divided by a predetermined word length to produce a final quantization value. The new linear, zig-zagged position of the current coefficient is converted to a two-dimensional display position. The final quantization value is written at the display position.
摘要翻译：用于在混合运动补偿和变换编码视频解码器中流水线可变长度解码和逆量化操作的方法包括将新码字映射到查找表以检索码字长度，零游程长度，和量化水平。从零游程长度和以前的零游程长度来识别当前系数的新的线性，Z字形位置。码字长度被添加到当前比特流位置以产生新的比特流位置。选择来自当前系数的新的线性，Z字形位置的量化矩阵系数。量化电平乘以预定值以产生量化乘积。在块间处理的情况下，将量化的电平符号值加到量化乘积上。在块内处理的情况下，量化乘积不包括量化等级符号。量化乘积乘以量化矩阵系数以形成导出的量化值。导出的量化值被预定的字长除以产生最终的量化值。电流系数的新的线性，Z字形位置被转换为二维显示位置。最终量化值被写入显示位置。

7. 发明授权

US06539059B1 Apparatus and method for efficiently scalable digital video decoding 有权
标题翻译：用于高效可扩展数字视频解码的装置和方法
公开(公告)号：US06539059B1
公开(公告)日：2003-03-25
申请号：US09518455
申请日：2000-03-02
申请人： Parthasarathy Sriram , Subramania I. Sudharsanan , Amit Gulati
发明人： Parthasarathy Sriram , Subramania I. Sudharsanan , Amit Gulati
IPC分类号： H04N712
CPC分类号： H04N19/90 , H04N19/172 , H04N19/174 , H04N19/176 , H04N19/177 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/61 , H04N19/70
摘要： An apparatus for decoding a Motion Compensated-Discrete Cosine Transform (MC-DCT) video stream includes an input port to receive an MC-DCT video stream with an associated hierarchy of data structures including a sequence data structure, a picture data structure, a slice data structure, and a macroblock data structure. A monitor processor splits the MC-DCT video stream into a set of video streams. A set of sub-processors processes the set of video streams. Each sub-processor has an assigned computational task performed on a specified hierarchical level of the associated hierarchy of data structures. Each sub-processor performs the assigned computational task with a designated data structure including all parameter data required at the specified hierarchical level.
摘要翻译：用于解码运动补偿离散余弦变换（MC-DCT）视频流的装置包括用于接收具有包括序列数据结构，图像数据结构，切片的数据结构的相关层级的MC-DCT视频流的输入端口数据结构和宏块数据结构。监视器处理器将MC-DCT视频流分解成一组视频流。一组子处理器处理视频流集合。每个子处理器具有在相关联的数据结构层级的指定层级上执行的分配的计算任务。每个子处理器使用指定的数据结构来执行分配的计算任务，包括在指定层次级别所需的所有参数数据。

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