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21. 发明申请

US20050205894A1 Method for variability constraints in design of integrated circuits especially digital circuits which includes timing closure upon placement and routing of digital circuit or network 审中-公开
标题翻译：集成电路设计特别是数字电路的可变性约束的方法，包括数字电路或网络放置和布线时的定时关闭
公开(公告)号：US20050205894A1
公开(公告)日：2005-09-22
申请号：US11080456
申请日：2005-03-16
申请人： Takashi Sumikawa , Kyoji Yamashita , Dai Motojima
发明人： Takashi Sumikawa , Kyoji Yamashita , Dai Motojima
IPC分类号： H01L21/822 , H01L21/82 , H01L27/02 , H01L27/04 , H01L27/10 , H01L27/118
CPC分类号： H01L27/0207 , H01L27/11807
摘要： In a standard cell, dummy transistors have p-type and n-type dummy gate electrodes. The dummy transistors are in an OFF state all the time. The gate length of each of the dummy gate electrodes is extended over an end portion of a diffusion region toward the inside of the standard cell. Thus, the total surface area and the total perimeter of respective gate electrodes of all transistors provided in the standard cell are increased. As a result, for example, even though shapes of gate electrodes of transistors vary between the standard cell and each of other standard cells, transistor characteristics are substantially equal among the standard cells. Therefore, variations in delays of signals generated between the standard cells can be suppressed.
摘要翻译：在标准单元中，虚拟晶体管具有p型和n型虚拟栅电极。虚拟晶体管一直处于OFF状态。每个虚拟栅电极的栅极长度在扩散区域的端部朝向标准单元的内部延伸。因此，提供在标准单元中的所有晶体管的各个栅电极的总表面积和总周长增加。结果，例如，即使晶体管的栅电极的形状在标准单元与其他标准单元中的每一个之间变化，晶体管特性在标准单元中基本相等。因此，可以抑制在标准单元之间产生的信号的延迟的变化。

22. 发明申请

US20050007120A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20050007120A1
公开(公告)日：2005-01-13
申请号：US10777068
申请日：2004-02-13
申请人： Kyoji Yamashita , Tatsuya Kunikiyo , Tetsuya Watanabe , Toshiki Kanamoto
发明人： Kyoji Yamashita , Tatsuya Kunikiyo , Tetsuya Watanabe , Toshiki Kanamoto
IPC分类号： G01R31/28 , H01L21/822 , H01L27/04 , G01R31/08
CPC分类号： G01R31/2884 , G01R31/2853
摘要： PMISFETs and NMISFETs are placed in a capacitance measuring circuit. Each of interconnects is connected via the corresponding PMISFET through a charging voltage supply part to a power supply pad and via the corresponding NMISFET through a current sampling part to a current-monitoring pad. A current I can be measured by bringing a probe of an ammeter into contact with the current-monitoring pad.
摘要翻译： PMISFET和NMISFET放置在电容测量电路中。每个互连通过相应的PMISFET通过充电电压供应部分连接到电源焊盘，并通过相应的NMISFET通过电流采样部分连接到电流监测焊盘。可以通过将电流表的探头与电流监测板接触来测量电流。

23. 发明授权

US5879983A Semiconductor device and method for manufacturing the same 失效
公开(公告)号：US5879983A
公开(公告)日：1999-03-09
申请号：US716571
申请日：1996-09-18
申请人： Mizuki Segawa , Toshiki Yabu , Takashi Uehara , Takashi Nakabayashi , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada
发明人： Mizuki Segawa , Toshiki Yabu , Takashi Uehara , Takashi Nakabayashi , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada
IPC分类号： H01L29/43 , H01L21/02 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/04 , H01L27/06 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/8242
CPC分类号： H01L27/11526 , H01L21/82345 , H01L27/0629 , H01L27/105 , H01L27/11543 , H01L28/40 , Y10S438/957
摘要： A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled. In the semiconductor device in which a transistor, a capacitive element, a resistive film and the like are provided, the occupied area can be reduced and the manufacturing cost can be cut down.

24. 发明授权

US5675168A Unsymmetrical MOS device having a gate insulator area offset from the source and drain areas, and ESD protection circuit including such a MOS device 失效
标题翻译：具有偏离源极和漏极区域的栅极绝缘体区域的非对称MOS器件，以及包括这种MOS器件的ESD保护电路
公开(公告)号：US5675168A
公开(公告)日：1997-10-07
申请号：US415928
申请日：1995-04-03
申请人： Kyoji Yamashita , Shinji Odanaka , Kazumi Kurimoto , Akira Hiroki , Isao Miyanaga , Atsushi Hori
发明人： Kyoji Yamashita , Shinji Odanaka , Kazumi Kurimoto , Akira Hiroki , Isao Miyanaga , Atsushi Hori
IPC分类号： H01L27/02 , H01L27/088 , H01L29/08 , H01L29/78 , H01L23/60
CPC分类号： H01L27/0266 , H01L27/088 , H01L29/0847 , H01L29/7835 , H01L2924/0002
摘要： An unsymmetrical MOS device is disclosed which includes a semiconductor layer of a first conductive type having a surface having a first area and a second area which is offset from the first area; a gate insulator layer located on the first area of the surface of the semiconductor layer; a gate electrode located on the gate insulator layer; and a source region of a second conductive type and a drain region of the second conductive type each located in the semiconductor layer below the second area of the surface. The electric resistance of an area between the first area of the surface and the surface of the source region is smaller than the electric resistance of an area between the first area of the surface and the surface of the drain region.
摘要翻译：公开了一种不对称MOS器件，其包括具有第一区域的表面的第一导电类型的半导体层和与第一区域偏移的第二区域; 位于所述半导体层表面的第一区域上的栅极绝缘体层; 位于栅极绝缘体层上的栅电极; 以及第二导电类型的源极区域和第二导电类型的漏极区域，每个位于该表面的第二区域下方的半导体层中。表面的第一区域和源区域的表面之间的区域的电阻小于表面的第一区域和漏极区域的表面之间的区域的电阻。

25. 发明授权

US08260031B2 Pattern inspection apparatus, pattern inspection method, and computer-readable recording medium storing a program 有权
标题翻译：图案检查装置，图案检查方法以及存储程序的计算机可读记录介质
公开(公告)号：US08260031B2
公开(公告)日：2012-09-04
申请号：US12347345
申请日：2008-12-31
申请人： Kyoji Yamashita
发明人： Kyoji Yamashita
IPC分类号： G06K9/00
CPC分类号： G06T7/001 , G06T2207/30148
摘要： A pattern inspection apparatus includes a magnification conversion unit to convert first sample optical image data to higher resolution second sample optical image data, a low-pass filter configured to filter first design image data which has a resolution N times that of the first sample optical image data, an optical filter which calculates third design image data by convolving the second design image data with an optical model function, a coefficient acquisition unit configured to acquire a coefficient of the predetermined optical model function using the second sample optical image data and the third design image data, an optical image acquisition unit configured to acquire actual optical image data of an inspection target workpiece, a reference image data generation unit configured to generate reference image data corresponding to the actual optical image data, and a comparison unit configured to compare the actual optical image data with the reference image data.
摘要翻译：图案检查装置包括：倍率转换单元，用于将第一样本光学图像数据转换为更高分辨率的第二样本光学图像数据;低通滤波器，被配置为对具有第一样本光学图像的分辨率的N倍的第一设计图像数据进行滤波数据，光滤波器，其通过利用光学模型函数卷积第二设计图像数据来计算第三设计图像数据;系数获取单元，被配置为使用第二样本光学图像数据和第三设计来获取预定光学模型函数的系数图像数据，被配置为获取检查对象工件的实际光学图像数据的光学图像获取单元，被配置为生成与实际光学图像数据相对应的参考图像数据的参考图像数据生成单元，以及比较单元，具有参考图像数据的光学图像数据。

26. 发明授权

US07792663B2 Circuit simulation method 有权
标题翻译：电路仿真方法
公开(公告)号：US07792663B2
公开(公告)日：2010-09-07
申请号：US11822781
申请日：2007-07-10
申请人： Daisaku Ikoma , Kyoji Yamashita , Yasuyuki Sahara , Katsuhiro Ootani , Tomoyuki Ishizu
发明人： Daisaku Ikoma , Kyoji Yamashita , Yasuyuki Sahara , Katsuhiro Ootani , Tomoyuki Ishizu
IPC分类号： G06F17/10
CPC分类号： G06F17/504 , G06F17/5022
摘要： A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.
摘要翻译：电路模拟装置具有获取关于晶体管的数据的模块，用于产生表示由隔离区域引起的晶体管有源区上的应力的影响的模型参数的模型参数生成单元，以及用于评估晶体管的特性的模拟执行单元使用与模型参数相关联的模拟程序。模型参数包括关于晶体管有源区的宽度的术语，关于外围有源区的宽度的术语，以及关于晶体管有源区和外围有源区之间的宽度的项。

27. 发明授权

US07562327B2 Mask layout design improvement in gate width direction 有权
标题翻译：面板布局设计改善了门宽方向
公开(公告)号：US07562327B2
公开(公告)日：2009-07-14
申请号：US11591452
申请日：2006-11-02
申请人： Shinsaku Sekido , Kyoji Yamashita , Katsuhiro Ootani , Yasuyuki Sahara , Daisaku Ikoma
发明人： Shinsaku Sekido , Kyoji Yamashita , Katsuhiro Ootani , Yasuyuki Sahara , Daisaku Ikoma
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , H01L21/823878 , H01L21/823892 , H01L29/41758
摘要： In a cell comprising an N well and a P well, a distance SP04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance from a well boundary to the center line of the contact N-type region is equal to SP04. A design on the P well is similar to that on the N well. Thereby, modeling of the transistor in the cell can be performed, taking into consideration an influence from resist in one direction. Also, by fabricating a cell array which satisfies the above-described conditions, design accuracy can be improved.
摘要翻译：在包括N阱和P阱的单元中，从接触N型区域的中心线到N阱的N阱端的距离SP04被设定为使晶体管不受影响的距离抗。从阱边界到接触N型区域的中心线的距离等于SP04。 P井的设计与N井相似。因此，考虑到在一个方向上的抗蚀剂的影响，可以对单元中的晶体管进行建模。此外，通过制造满足上述条件的单元阵列，可以提高设计精度。

28. 发明授权

US07519593B2 Data searching system, method of synchronizing metadata and data searching apparatus 有权
标题翻译：数据搜索系统，同步元数据和数据搜索装置的方法
公开(公告)号：US07519593B2
公开(公告)日：2009-04-14
申请号：US11553711
申请日：2006-10-27
申请人： Kazuko Abe , Junichi Yamamoto , Rei Yano , Masataka Yamada , Yasuhide Kurosaki , Michiyo Ikegami , Kyoji Yamashita , Kouji Gouda
发明人： Kazuko Abe , Junichi Yamamoto , Rei Yano , Masataka Yamada , Yasuhide Kurosaki , Michiyo Ikegami , Kyoji Yamashita , Kouji Gouda
IPC分类号： G06F7/00 , G06F17/30 , G06F12/00
CPC分类号： G06F17/30964 , Y10S707/99933 , Y10S707/99936 , Y10S707/99953
摘要： A data searching unit 12 of a data searching apparatus 10 Obtains, according to a searching request including a search condition specified by a data searching application 16, metadata which satisfy the search condition from a data storage unit 11, and instructs an external communication unit 15 to request searching of data to a data providing apparatus 20 with the same search condition.
摘要翻译：数据搜索装置10的数据搜索单元12根据包括由数据搜索应用16指定的搜索条件的搜索请求，从数据存储单元11获得满足搜索条件的元数据，并指示外部通信单元15 请求搜索具有相同搜索条件的数据提供装置20。

29. 发明申请

US20080166054A1 PATTERN INSPECTION APPARATUS 有权
标题翻译：图案检查装置
公开(公告)号：US20080166054A1
公开(公告)日：2008-07-10
申请号：US12040541
申请日：2008-02-29
申请人： Hideo Tsuchiya , Kyoji Yamashita , Toshiyuki Watanabe , Ikunao Isomura , Toru Tojo , Yasushi Sanada
发明人： Hideo Tsuchiya , Kyoji Yamashita , Toshiyuki Watanabe , Ikunao Isomura , Toru Tojo , Yasushi Sanada
IPC分类号： G06K9/46
CPC分类号： G06T7/0004 , G06T2207/30148
摘要： A pattern inspection apparatus uses a die-to-database comparison method which compares detected pattern data obtained from an optical image of a pattern of a plate to be inspected with first reference pattern data obtained from designed pattern data in combination with a die-to-die comparison method which compares the detected pattern data with second reference pattern data obtained by detecting an area to be a basis for repetition. A computer detects presence of a plurality of repeated pattern areas from layout information contained in the designed pattern data, reads the arrangement, the number, the dimension and the repeated pitch of the repeated pattern areas, and automatically fetches an inspection area of the die-to-die comparison method.
摘要翻译：图案检查装置使用芯片对数据库比较方法，将从被检查板的图案的光学图像获得的检测图案数据与从设计图案数据获得的第一参考图案数据结合，芯片比较方法，其将检测到的图案数据与通过检测作为重复基础的区域获得的第二参考图案数据进行比较。计算机从包含在设计图案数据中的布局信息中检测多个重复图案区域的存在，读取重复图案区域的布置，数量，尺寸和重复间距，并且自动取出模具数据的检查区域，对比方法。

30. 发明申请

US20080072199A1 Method for designing semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路设计方法
公开(公告)号：US20080072199A1
公开(公告)日：2008-03-20
申请号：US11709749
申请日：2007-02-23
申请人： Kyoji Yamashita , Daisaku Ikoma , Shinji Watanabe , Katsuhiro Ootani
发明人： Kyoji Yamashita , Daisaku Ikoma , Shinji Watanabe , Katsuhiro Ootani
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The effective distance Deff_i between a well boundary and an active region of a transistor is used as a parameter for expressing a well proximity effect. For example, a delay library is created using the rising time Tslew of a signal input to the gate, load capacitance Cload at the output side and Deff_i. The use of the effective distance Deff_i between the well boundary and the transistor allows very simple modeling to be accurately performed, so that a gate-level simulation considering a well proximity effect at an LSI level is enabled.
摘要翻译：使用晶体管的阱边界和有源区之间的有效距离Deff_i作为用于表示良好邻近效应的参数。例如，使用输入到门的信号的上升时间Tslew，输出侧的负载电容Cload和Deff_i来创建延迟库。在井边界和晶体管之间使用有效距离Deff_i允许精确地执行非常简单的建模，使得考虑到在LSI级别的良好邻近效应的栅极级仿真是可以实现的。

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