专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050205894A1 Method for variability constraints in design of integrated circuits especially digital circuits which includes timing closure upon placement and routing of digital circuit or network 审中-公开
标题翻译：集成电路设计特别是数字电路的可变性约束的方法，包括数字电路或网络放置和布线时的定时关闭
公开(公告)号：US20050205894A1
公开(公告)日：2005-09-22
申请号：US11080456
申请日：2005-03-16
申请人： Takashi Sumikawa , Kyoji Yamashita , Dai Motojima
发明人： Takashi Sumikawa , Kyoji Yamashita , Dai Motojima
IPC分类号： H01L21/822 , H01L21/82 , H01L27/02 , H01L27/04 , H01L27/10 , H01L27/118
CPC分类号： H01L27/0207 , H01L27/11807
摘要： In a standard cell, dummy transistors have p-type and n-type dummy gate electrodes. The dummy transistors are in an OFF state all the time. The gate length of each of the dummy gate electrodes is extended over an end portion of a diffusion region toward the inside of the standard cell. Thus, the total surface area and the total perimeter of respective gate electrodes of all transistors provided in the standard cell are increased. As a result, for example, even though shapes of gate electrodes of transistors vary between the standard cell and each of other standard cells, transistor characteristics are substantially equal among the standard cells. Therefore, variations in delays of signals generated between the standard cells can be suppressed.
摘要翻译：在标准单元中，虚拟晶体管具有p型和n型虚拟栅电极。虚拟晶体管一直处于OFF状态。每个虚拟栅电极的栅极长度在扩散区域的端部朝向标准单元的内部延伸。因此，提供在标准单元中的所有晶体管的各个栅电极的总表面积和总周长增加。结果，例如，即使晶体管的栅电极的形状在标准单元与其他标准单元中的每一个之间变化，晶体管特性在标准单元中基本相等。因此，可以抑制在标准单元之间产生的信号的延迟的变化。

2. 发明申请

US20080105904A1 Method for variability constraints in design of integrated circuits especially digital circuits which includes timing closure upon placement and routing of digital circuit or network 审中-公开
标题翻译：集成电路设计特别是数字电路的可变性约束的方法，包括数字电路或网络放置和布线时的定时关闭
公开(公告)号：US20080105904A1
公开(公告)日：2008-05-08
申请号：US11907320
申请日：2007-10-11
申请人： Takashi Sumikawa , Kyoji Yamashita , Dai Motojima
发明人： Takashi Sumikawa , Kyoji Yamashita , Dai Motojima
IPC分类号： H01L29/00
CPC分类号： H01L27/0207 , H01L27/11807
摘要： In a standard cell, dummy transistors have p-type and n-type dummy gate electrodes. The dummy transistors are in an OFF state all the time. The gate length of each of the dummy gate electrodes is extended over an end portion of a diffusion region toward the inside of the standard cell. Thus, the total surface area and the total perimeter of respective gate electrodes of all transistors provided in the standard cell are increased. As a result, for example, even though shapes of gate electrodes of transistors vary between the standard cell and each of other standard cells, transistor characteristics are substantially equal among the standard cells. Therefore, variations in delays of signals generated between the standard cells can be suppressed.
摘要翻译：在标准单元中，虚拟晶体管具有p型和n型虚拟栅电极。虚拟晶体管一直处于OFF状态。每个虚拟栅电极的栅极长度在扩散区域的端部朝向标准单元的内部延伸。因此，提供在标准单元中的所有晶体管的各个栅电极的总表面积和总周长增加。结果，例如，即使晶体管的栅电极的形状在标准单元与其他标准单元中的每一个之间变化，晶体管特性在标准单元中基本相等。因此，可以抑制在标准单元之间产生的信号的延迟的变化。

3. 发明授权

US08143725B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08143725B2
公开(公告)日：2012-03-27
申请号：US12650733
申请日：2009-12-31
申请人： Dai Motojima
发明人： Dai Motojima
IPC分类号： H01L29/40
CPC分类号： H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first interconnect 31; a second interconnect 32 which is formed in a different interconnect layer from that of the first interconnect 31, and which has a wider line width than that of the first interconnect 31; and first and second plugs 51 and 52 which are formed in a region where the first and second interconnects 31 and 32 extend in the same direction so as to overlap one above the other, and which electrically connect the first and second interconnects 31 and 32. The first plug 51 has a larger base area than that of the second plug 52, and is formed on an end side of the first interconnect 31 with respect to the second plug 52.
摘要翻译：半导体器件包括第一互连31; 第二互连件32，其形成在与第一互连件31不同的互连层中，并且具有比第一互连件31宽的线宽; 以及第一和第二插头51和52，其形成在第一和第二互连件31和32沿相同方向延伸以便彼此重叠的区域中，并且将第一和第二互连件31和32电连接。第一插头51具有比第二插头52更大的基座面积，并且相对于第二插头52形成在第一互连件31的端侧上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式