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21. 发明授权

US5786255A Method of forming a metallic oxide semiconductor 失效
标题翻译：形成金属氧化物半导体的方法
公开(公告)号：US5786255A
公开(公告)日：1998-07-28
申请号：US863426
申请日：1997-05-27
申请人： Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
IPC分类号： H01L21/336 , H01L29/417
CPC分类号： H01L29/66583 , H01L29/41775 , H01L29/41783
摘要： A method of forming MOS components provides that after the formation of the gate and the doped source/drain regions, a polysilicon layer is deposited and planarized using a chemical-mechanical polishing method. The resulting unremoved polysilicon layer acts as source/drain terminals. Through these arrangements, the ion doped source/drain regions will have shallow junctions, yet their junction integrity will not be compromised by subsequent contact window etching and metallization processes. Furthermore, the front-end processes for forming the MOS component provide a good planar surface that offers great convenience for the performance of subsequent back-end processes.
摘要翻译：形成MOS部件的方法提供了在形成栅极和掺杂源极/漏极区域之后，使用化学 - 机械抛光方法沉积并平坦化多晶硅层。所产生的未移动的多晶硅层用作源极/漏极端子。通过这些布置，离子掺杂的源极/漏极区域将具有浅结，但是它们的连接完整性将不会被随后的接触窗蚀刻和金属化处理所影响。此外，用于形成MOS部件的前端工艺提供了良好的平面表面，为后续工艺的性能提供了极大的便利。

22. 发明申请

US20080233706A1 MANUFACTURING METHOD OF DYNAMIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：动态随机存取存储器的制造方法
公开(公告)号：US20080233706A1
公开(公告)日：2008-09-25
申请号：US12111980
申请日：2008-04-30
申请人： Jih-Wen Chou , Yu-Chi Chen
发明人： Jih-Wen Chou , Yu-Chi Chen
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L27/10867 , H01L29/945
摘要： A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer disposed on the surface of the substrate at two sides of the gate structure. The depth of the second trench is smaller than the depth of the first trench, and the second trench partially overlaps with the first trench. The conductive layer disposed in the second trench is electrically connected with the conductive layer of the deep trench capacitor. The gate structure is disposed on the substrate. The conductive layer at one side of the gate structure is electrically connected with the conductive layer disposed in the second trench.
摘要翻译：提供了动态随机存取存储器（DRAM）。动态随机存取存储器包括设置在衬底的第一沟槽中的深沟槽电容器，设置在衬底的第二沟槽中的导电层，栅极结构和设置在衬底的表面上的导电层，门结构。第二沟槽的深度小于第一沟槽的深度，第二沟槽与第一沟槽部分重叠。设置在第二沟槽中的导电层与深沟槽电容器的导电层电连接。栅极结构设置在基板上。栅极结构一侧的导电层与设置在第二沟槽中的导电层电连接。

23. 发明授权

US07394124B2 Dynamic random access memory device 有权
标题翻译：动态随机存取存储器
公开(公告)号：US07394124B2
公开(公告)日：2008-07-01
申请号：US11307424
申请日：2006-02-07
申请人： Jih-Wen Chou , Yu-Chi Chen
发明人： Jih-Wen Chou , Yu-Chi Chen
IPC分类号： H01L29/94
CPC分类号： H01L27/1087 , H01L27/10867 , H01L29/945
摘要： A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer disposed on the surface of the substrate at two sides of the gate structure. The depth of the second trench is smaller than the depth of the first trench, and the second trench partially overlaps with the first trench. The conductive layer disposed in the second trench is electrically connected with the conductive layer of the deep trench capacitor. The gate structure is disposed on the substrate. The conductive layer at one side of the gate structure is electrically connected with the conductive layer disposed in the second trench.
摘要翻译：提供了动态随机存取存储器（DRAM）。动态随机存取存储器包括设置在衬底的第一沟槽中的深沟槽电容器，设置在衬底的第二沟槽中的导电层，栅极结构和设置在衬底的表面上的导电层，门结构。第二沟槽的深度小于第一沟槽的深度，第二沟槽与第一沟槽部分重叠。设置在第二沟槽中的导电层与深沟槽电容器的导电层电连接。栅极结构设置在基板上。栅极结构一侧的导电层与设置在第二沟槽中的导电层电连接。

24. 发明申请

US20070249123A1 Method of fabricating a recess channel transistor 有权
标题翻译：制造凹槽通道晶体管的方法
公开(公告)号：US20070249123A1
公开(公告)日：2007-10-25
申请号：US11491137
申请日：2006-07-24
申请人： Jih-Wen Chou , Chih-Hsun Chu , Hsiu-Chuan Shu
发明人： Jih-Wen Chou , Chih-Hsun Chu , Hsiu-Chuan Shu
IPC分类号： H01L21/336 , H01L21/425 , H01L21/3205
CPC分类号： H01L21/26586 , H01L21/28114 , H01L29/42376 , H01L29/66621 , H01L29/78 , Y10S438/981
摘要： A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a tilt angle on sidewalls of the trench to form an implant area. A thermal oxidation process is performed to form an oxide layer. The oxide layer comprises a first thickness on the source/drain in the sidewalls of the trench and a second thickness on the other portion in the sidewalls of the trench.
摘要翻译：提供一种制造凹槽通道晶体管的方法。首先，在掺杂半导体层和基板上形成硬掩模。蚀刻掺杂半导体层和衬底以形成沟槽并且在掺杂半导体层中限定源极/漏极。在沟槽的侧壁上以倾斜角度执行植入工艺以形成植入区域。进行热氧化处理以形成氧化物层。氧化物层包括在沟槽的侧壁中的源极/漏极上的第一厚度和在沟槽的侧壁中的另一部分上的第二厚度。

25. 发明申请

US20070012994A1 SEMICONDUTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070012994A1
公开(公告)日：2007-01-18
申请号：US11162727
申请日：2005-09-21
申请人： Jih-Wen Chou , Chih-Hsun Chu
发明人： Jih-Wen Chou , Chih-Hsun Chu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/0653 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device is provided. The semiconductor device has a gate structure, a source region, a drain region, and a pair of dielectric barrier layers. The gate structure is formed on a substrate. The source region and the drain region are formed in the substrate next to the gate structure, and a channel region is formed between the source region and the drain region underneath the gate structure. The pair of dielectric barrier layers is respectively formed in the substrate underneath the gate structure between the source region and the drain region. The dielectric barrier layers are used for reducing the drain induced barrier lowering effect in a nanometer scale device.
摘要翻译：提供半导体器件。半导体器件具有栅极结构，源极区，漏极区和一对介电阻挡层。栅极结构形成在基板上。源极区域和漏极区域形成在栅极结构旁边的衬底中，并且在栅极结构之下的源极区域和漏极区域之间形成沟道区域。一对电介质阻挡层分别形成在源极区域和漏极区域之间的栅极结构下方的衬底中。电介质阻挡层用于在纳米级装置中降低漏极引发的阻挡层降低效果。

26. 发明授权

US06190981B1 Method for fabricating metal oxide semiconductor 有权
标题翻译：金属氧化物半导体的制造方法
公开(公告)号：US06190981B1
公开(公告)日：2001-02-20
申请号：US09243740
申请日：1999-02-03
申请人： Tony Lin , Jih-Wen Chou
发明人： Tony Lin , Jih-Wen Chou
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L29/4983 , H01L29/4991 , H01L29/665
摘要： A method of for fabrication a metal oxide semiconductor transistor is described. A substrate with an isolation structure thereon is provided. A gate oxide layer is formed on the substrate. A polysilicon layer is formed on the gate oxide layer. The polysilicon layer is patterned to form a gate on the gate oxide layer. An offset spacer is formed on the sidewall of the gate. A source/drain extension is formed in the substrate on two sides of the gate by ion implantation. An insulating spacer is formed on the sidewall of the offset spacer. A source/drain region is formed in the substrate by ion implantation using the gate, the offset spacer and the insulating spacer as a mask. Salicide is formed on the gate and on the surface of the source/drain region. After forming the salicide, the offset spacer is removed. After removing the offset spacer, a halo doped region is formed in the substrate below the source/drain extension by ion implantation.
摘要翻译：描述了制造金属氧化物半导体晶体管的方法。提供其上具有隔离结构的基板。在衬底上形成栅氧化层。在栅氧化层上形成多晶硅层。图案化多晶硅层以在栅极氧化物层上形成栅极。在门的侧壁上形成偏移间隔物。通过离子注入在栅极两侧的衬底中形成源极/漏极延伸。绝缘间隔件形成在偏移间隔件的侧壁上。通过使用栅极，偏移间隔物和绝缘间隔物作为掩模的离子注入在衬底中形成源极/漏极区。在栅极和源极/漏极区域的表面上形成硅化物。在形成自对准硅胶后，去除偏移间隔物。在去除偏移间隔物之后，通过离子注入在源极/漏极延伸部下方的衬底中形成光晕掺杂区域。

27. 发明授权

US06171895B2 Fabrication of buried channel devices with shallow junction depth 失效
标题翻译：具有浅结深度的埋地通道器件的制造
公开(公告)号：US06171895B2
公开(公告)日：2001-01-09
申请号：US09173547
申请日：1998-10-16
申请人： Jih-Wen Chou , Shih-Wei Sun
发明人： Jih-Wen Chou , Shih-Wei Sun
IPC分类号： H01L218238
CPC分类号： H01L29/7838 , H01L21/26513 , H01L21/8238 , H01L21/823807 , H01L27/0927 , H01L29/66477
摘要： The channel doping profile of a PMOS field effect transistor consists of a shallow distribution of a P-type dopant as a threshold adjust implant, a deeper distribution of an N-type dopant as an buried channel stop implant and a still deeper implantation of an N-type dopant as an antipunchthrough implant. A junction is formed between the P-type threshold adjust implant and the N-type buried channel stop implant at a relatively shallow depth so that the depth of the buried channel region is limited by the buried channel stop implant, reducing the short channel effect. The channel doping profile is formed so that diffsion of impurities from the channel region to the gate oxide is prevented. The buried channel stop implant is made first through a sacrificial oxide layer. The sacrificial oxide is etched and a gate oxide layer and a thin film of polysilicon are deposited on the surface of the gate oxide. Both the threshold implant and the antipunchthrough implant are made through the thin polysilicon layer and the gate oxide layer. After the channel doping profile is defined, additional gate material is deposited and device construction is completed in the normal manner.
摘要翻译： PMOS场效应晶体管的沟道掺杂分布由P型掺杂剂的浅分布组成，作为阈值调整注入，作为掩埋沟道停止注入的N型掺杂剂的深度分布以及N 型掺杂剂作为抗穿通植入物。在P型阈值调整植入物和N型埋入通道停止植入物之间形成一个相对较浅深度的结，使得掩埋沟道区域的深度受到掩埋沟道阻挡植入物的限制，从而减少短沟道效应。形成通道掺杂分布，从而防止杂质从沟道区域到栅极氧化物的杂化。首先通过牺牲氧化物层制造掩埋沟道阻挡植入物。蚀刻牺牲氧化物，并且栅极氧化物层和多晶硅薄膜沉积在栅极氧化物的表面上。通过薄多晶硅层和栅极氧化物层制造阈值植入和抗穿通植入物两者。在限定沟道掺杂分布之后，沉积额外的栅极材料并以正常方式完成器件结构。

28. 发明授权

US6156126A Method for reducing or avoiding the formation of a silicon recess in SDE junction regions 有权
标题翻译：用于减少或避免在SDE连接区域中形成硅凹槽的方法
公开(公告)号：US6156126A
公开(公告)日：2000-12-05
申请号：US484790
申请日：2000-01-18
申请人： Tung-Po Chen , Jih-Wen Chou
发明人： Tung-Po Chen , Jih-Wen Chou
IPC分类号： G03F7/42 , H01L21/265 , H01L21/306 , H01L21/336 , B08B3/04
CPC分类号： H01L21/02052 , H01L21/26513 , H01L29/6659 , G03F7/422 , Y10S134/902
摘要： A method for cleaning a silicon wafer. The method includes intentionally exposing the wafer into a volatile solvent with a polarity between about 2 and 4, whereby the wafer is cleaned by the solvent such that the formation of silicon recesses in source/drain extension regions on the silicon wafer can be prevented or avoided.
摘要翻译：一种清洗硅晶片的方法。该方法包括将晶片有意地暴露在极性为约2和4之间的挥发性溶剂中，由此通过溶剂清洁晶片，从而可以防止或避免在硅晶片上的源极/漏极延伸区域中形成硅凹槽。

29. 发明授权

US6033958A Method of fabricating dual voltage MOS transistors 失效
标题翻译：制造双电压MOS晶体管的方法
公开(公告)号：US6033958A
公开(公告)日：2000-03-07
申请号：US108107
申请日：1998-06-30
申请人： Jih-Wen Chou , Cheng-Han Huang
发明人： Jih-Wen Chou , Cheng-Han Huang
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462
摘要： A method of forming dual voltage MOS transistors includes first forming a mask layer, covering one of the at least two device regions and exposing another one of the two device regions. A gate oxide layer is then formed by thermal oxidation on the exposed device region. After removing the mask layer and exposing another gate oxide formed therebeneath, polysilicon gates for both of the two device regions can be formed.
摘要翻译：形成双电压MOS晶体管的方法包括：首先形成掩模层，覆盖所述至少两个器件区域中的一个并暴露两个器件区域中的另一个。然后通过在暴露的器件区域上的热氧化形成栅极氧化物层。在去除掩模层并暴露另外形成的栅极氧化物之后，可以形成用于两个器件区域的多晶硅栅极。

30. 发明授权

US6025234A Method for manufacturing thick gate oxide device 失效
标题翻译：厚栅极氧化器件的制造方法
公开(公告)号：US6025234A
公开(公告)日：2000-02-15
申请号：US992675
申请日：1997-12-17
申请人： Jih-Wen Chou
发明人： Jih-Wen Chou
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823462 , Y10S438/931
摘要： A method for forming devices having a thick gate oxide. The method comprises the steps of providing a substrate having different device areas already defined thereon through shallow trench isolation, then forming a first gate oxide layer over the substrate. Next, a silicon nitride layer is formed over the first gate oxide layer, then patterned using a mask to selectively expose the first gate oxide layer in the thick gate oxide area. Subsequently, a thermal oxidation is performed to directly grow an oxide layer over the first gate oxide layer to form a thicker second gate oxide layer. Since no gate oxide layer is removed in this invention, the distribution of ions implanted in previous processing steps will remain unchanged. Therefore, the fabricated devices will have more stable properties and better reliability.
摘要翻译：一种用于形成具有厚栅极氧化物的器件的方法。该方法包括以下步骤：通过浅沟槽隔离提供具有已经在其上定义的不同器件区域的衬底，然后在衬底上形成第一栅极氧化物层。接下来，在第一栅极氧化物层上形成氮化硅层，然后使用掩模进行图案化以选择性地暴露厚栅极氧化物区域中的第一栅极氧化物层。随后，进行热氧化以在第一栅极氧化物层上直接生长氧化物层，以形成较厚的第二栅极氧化物层。由于在本发明中没有去除栅极氧化物层，所以在先前的处理步骤中植入的离子的分布将保持不变。因此，制造的器件将具有更稳定的性能和更好的可靠性。

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