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1. 发明授权

US07494865B2 Fabrication method of metal oxide semiconductor transistor 有权
标题翻译：金属氧化物半导体晶体管的制造方法
公开(公告)号：US07494865B2
公开(公告)日：2009-02-24
申请号：US11459360
申请日：2006-07-23
申请人： Yu-Chi Chen , Jih-Wen Chou , Frank Chen
发明人： Yu-Chi Chen , Jih-Wen Chou , Frank Chen
IPC分类号： H01L21/8242
CPC分类号： H01L29/66628 , H01L21/28061 , H01L29/66621 , H01L29/7834
摘要： A manufacturing method of metal oxide semiconductor transistor is provided. A substrate is provided. A source/drain extension region is formed in the substrate. A pad material layer with low dielectric constant is formed on the substrate. A trench is formed in the substrate and the pad material layer. A gate dielectric layer is formed on the surface of the substrate in the trench. A stacked gate structure is formed in the trench, wherein the top surface of a conductive layer of the stacked gate structure is higher than the surface of the pad material layer. A spacer material layer is formed conformably on the substrate. Portions of the spacer material layer and the pad material layer are removed so as to form a pair of first spacers and a pair of pad blocks. A source/drain is formed on the substrate beside the stacked gate structure.
摘要翻译：提供了金属氧化物半导体晶体管的制造方法。提供基板。源极/漏极延伸区域形成在衬底中。在基板上形成具有低介电常数的焊盘材料层。在衬底和衬垫材料层中形成沟槽。栅极电介质层形成在沟槽中的衬底的表面上。在沟槽中形成堆叠的栅极结构，其中层叠栅极结构的导电层的顶表面高于焊盘材料层的表面。衬垫材料层在衬底上顺应地形成。去除间隔材料层和垫材料层的一部分，以形成一对第一间隔物和一对垫块。源极/漏极形成在堆叠栅极结构旁边的衬底上。

2. 发明申请

US20070267691A1 METAL OXIDE SEMICONDUCTOR TRANSISTOR AND FABRICATION METHOD THEREOF 有权
标题翻译：金属氧化物半导体晶体管及其制造方法
公开(公告)号：US20070267691A1
公开(公告)日：2007-11-22
申请号：US11459360
申请日：2006-07-23
申请人： Yu-Chi Chen , Jih-Wen Chou , Frank Chen
发明人： Yu-Chi Chen , Jih-Wen Chou , Frank Chen
IPC分类号： H01L29/94
CPC分类号： H01L29/66628 , H01L21/28061 , H01L29/66621 , H01L29/7834
摘要： A manufacturing method of metal oxide semiconductor transistor is provided. A substrate is provided. A source/drain extension region is formed in the substrate. A pad material layer with low dielectric constant is formed on the substrate. A trench is formed in the substrate and the pad material layer. A gate dielectric layer is formed on the surface of the substrate in the trench. A stacked gate structure is formed in the trench, wherein the top surface of a conductive layer of the stacked gate structure is higher than the surface of the pad material layer. A spacer material layer is formed conformably on the substrate. Portions of the spacer material layer and the pad material layer are removed so as to form a pair of first spacers and a pair of pad blocks. A source/drain is formed on the substrate beside the stacked gate structure.
摘要翻译：提供了金属氧化物半导体晶体管的制造方法。提供基板。源极/漏极延伸区域形成在衬底中。在基板上形成具有低介电常数的焊盘材料层。在衬底和衬垫材料层中形成沟槽。栅极电介质层形成在沟槽中的衬底的表面上。在沟槽中形成堆叠的栅极结构，其中层叠栅极结构的导电层的顶表面高于焊盘材料层的表面。衬垫材料层在衬底上顺应地形成。去除间隔材料层和垫材料层的一部分，以形成一对第一间隔物和一对垫块。源极/漏极形成在堆叠栅极结构旁边的衬底上。

3. 发明申请

US20080233706A1 MANUFACTURING METHOD OF DYNAMIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：动态随机存取存储器的制造方法
公开(公告)号：US20080233706A1
公开(公告)日：2008-09-25
申请号：US12111980
申请日：2008-04-30
申请人： Jih-Wen Chou , Yu-Chi Chen
发明人： Jih-Wen Chou , Yu-Chi Chen
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L27/10867 , H01L29/945
摘要： A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer disposed on the surface of the substrate at two sides of the gate structure. The depth of the second trench is smaller than the depth of the first trench, and the second trench partially overlaps with the first trench. The conductive layer disposed in the second trench is electrically connected with the conductive layer of the deep trench capacitor. The gate structure is disposed on the substrate. The conductive layer at one side of the gate structure is electrically connected with the conductive layer disposed in the second trench.
摘要翻译：提供了动态随机存取存储器（DRAM）。动态随机存取存储器包括设置在衬底的第一沟槽中的深沟槽电容器，设置在衬底的第二沟槽中的导电层，栅极结构和设置在衬底的表面上的导电层，门结构。第二沟槽的深度小于第一沟槽的深度，第二沟槽与第一沟槽部分重叠。设置在第二沟槽中的导电层与深沟槽电容器的导电层电连接。栅极结构设置在基板上。栅极结构一侧的导电层与设置在第二沟槽中的导电层电连接。

4. 发明授权

US07394124B2 Dynamic random access memory device 有权
标题翻译：动态随机存取存储器
公开(公告)号：US07394124B2
公开(公告)日：2008-07-01
申请号：US11307424
申请日：2006-02-07
申请人： Jih-Wen Chou , Yu-Chi Chen
发明人： Jih-Wen Chou , Yu-Chi Chen
IPC分类号： H01L29/94
CPC分类号： H01L27/1087 , H01L27/10867 , H01L29/945
摘要： A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer disposed on the surface of the substrate at two sides of the gate structure. The depth of the second trench is smaller than the depth of the first trench, and the second trench partially overlaps with the first trench. The conductive layer disposed in the second trench is electrically connected with the conductive layer of the deep trench capacitor. The gate structure is disposed on the substrate. The conductive layer at one side of the gate structure is electrically connected with the conductive layer disposed in the second trench.
摘要翻译：提供了动态随机存取存储器（DRAM）。动态随机存取存储器包括设置在衬底的第一沟槽中的深沟槽电容器，设置在衬底的第二沟槽中的导电层，栅极结构和设置在衬底的表面上的导电层，门结构。第二沟槽的深度小于第一沟槽的深度，第二沟槽与第一沟槽部分重叠。设置在第二沟槽中的导电层与深沟槽电容器的导电层电连接。栅极结构设置在基板上。栅极结构一侧的导电层与设置在第二沟槽中的导电层电连接。

5. 发明申请

US20070085123A1 DYNAMIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：动态随机存取存储器及其制造方法
公开(公告)号：US20070085123A1
公开(公告)日：2007-04-19
申请号：US11307424
申请日：2006-02-07
申请人： Jih-Wen Chou , Yu-Chi Chen
发明人： Jih-Wen Chou , Yu-Chi Chen
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L27/1087 , H01L27/10867 , H01L29/945
摘要： A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer disposed on the surface of the substrate at two sides of the gate structure. The depth of the second trench is smaller than the depth of the first trench, and the second trench partially overlaps with the first trench. The conductive layer disposed in the second trench is electrically connected with the conductive layer of the deep trench capacitor. The gate structure is disposed on the substrate. The conductive layer at one side of the gate structure is electrically connected with the conductive layer disposed in the second trench.
摘要翻译：提供了动态随机存取存储器（DRAM）。动态随机存取存储器包括设置在衬底的第一沟槽中的深沟槽电容器，设置在衬底的第二沟槽中的导电层，栅极结构和设置在衬底的表面上的导电层，门结构。第二沟槽的深度小于第一沟槽的深度，第二沟槽与第一沟槽部分重叠。设置在第二沟槽中的导电层与深沟槽电容器的导电层电连接。栅极结构设置在基板上。栅极结构一侧的导电层与设置在第二沟槽中的导电层电连接。

6. 发明授权

US07531438B2 Method of fabricating a recess channel transistor 有权
标题翻译：制造凹槽通道晶体管的方法
公开(公告)号：US07531438B2
公开(公告)日：2009-05-12
申请号：US11491137
申请日：2006-07-24
申请人： Jih-Wen Chou , Chih-Hsun Chu , Hsiu-Chuan Shu
发明人： Jih-Wen Chou , Chih-Hsun Chu , Hsiu-Chuan Shu
IPC分类号： H01L21/3205
CPC分类号： H01L21/26586 , H01L21/28114 , H01L29/42376 , H01L29/66621 , H01L29/78 , Y10S438/981
摘要： A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a tilt angle on sidewalls of the trench to form an implant area. A thermal oxidation process is performed to form an oxide layer. The oxide layer comprises a first thickness on the source/drain in the sidewalls of the trench and a second thickness on the other portion in the sidewalls of the trench.
摘要翻译：提供一种制造凹槽通道晶体管的方法。首先，在掺杂半导体层和基板上形成硬掩模。蚀刻掺杂半导体层和衬底以形成沟槽并且在掺杂半导体层中限定源极/漏极。在沟槽的侧壁上以倾斜角度执行植入工艺以形成植入区域。进行热氧化处理以形成氧化物层。氧化物层包括在沟槽的侧壁中的源极/漏极上的第一厚度和在沟槽的侧壁中的另一部分上的第二厚度。

7. 发明授权

US06228730B1 Method of fabricating field effect transistor 有权
标题翻译：制作场效应晶体管的方法
公开(公告)号：US06228730B1
公开(公告)日：2001-05-08
申请号：US09301211
申请日：1999-04-28
申请人： Tung-Po Chen , Jih-Wen Chou
发明人： Tung-Po Chen , Jih-Wen Chou
IPC分类号： H01L21336
CPC分类号： H01L29/66628 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/7834
摘要： A method of fabricating a field effect transistor, wherein a substrate with a gate is provided. A liner oxide layer and a first spacer are formed adjacent to the sides of the gate. An epitaxial silicon layer is formed at both sides of the gate in the substrate, while a shallow source/drain (S/D) extension junction is formed in the substrate below the epitaxial silicon layer. An oxide layer and a second spacer are formed to be closely connected to the first spacer and form the S/D region below the epitaxial silicon layer. A part of the epitaxial silicon layer is then transformed into a metal silicide layer, so as to complete the process of the field effect transistor.
摘要翻译：一种制造场效应晶体管的方法，其中提供具有栅极的基板。衬套氧化物层和第一间隔件邻近栅极的侧面形成。在衬底的栅极的两侧形成外延硅层，而在外延硅层下面的衬底中形成浅源极/漏极（S / D）延伸结。形成氧化物层和第二间隔物以紧密地连接到第一间隔物并在外延硅层下面形成S / D区。然后将外延硅层的一部分转变成金属硅化物层，以完成场效应晶体管的工艺。

8. 发明授权

US06200870B1 Method for forming gate 有权
标题翻译：浇口形成方法
公开(公告)号：US06200870B1
公开(公告)日：2001-03-13
申请号：US09189355
申请日：1998-11-09
申请人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/28061 , H01L21/28247
摘要： A method for forming a gate that improves the quality of the gate includes sequentially forming a gate oxide layer, a polysilicon layer, a conductive layer and a masking layer on a substrate. Thereafter, the masking layer, the conductive layer, the polysilicon layer and the gate oxide layer are patterned to form the gate. Then, a passivation layer, for increasing the thermal stability and the chemical stability of the gate, is formed on the sidewall of the conductive layer by ion implantation with nitrogen cations. The nitrogen cations are doped into the substrate, under the gate oxide layer, by ion implantation, which can improve the penetration of the phosphorus ions.
摘要翻译：用于形成提高栅极质量的栅极的方法包括在衬底上顺序地形成栅极氧化物层，多晶硅层，导电层和掩模层。此后，对掩模层，导电层，多晶硅层和栅极氧化物层进行图案化以形成栅极。然后，通过用氮阳离子的离子注入，在导电层的侧壁上形成用于增加栅极的热稳定性和化学稳定性的钝化层。氮阳离子通过离子注入在栅极氧化物层下方掺杂到衬底中，这可以改善磷离子的渗透。

9. 发明授权

US06174791B1 Method for a pre-amorphization 失效
标题翻译：前非晶化方法
公开(公告)号：US06174791B1
公开(公告)日：2001-01-16
申请号：US09276294
申请日：1999-03-25
申请人： Tony Lin , Jih-Wen Chou , C. C. Hsue
发明人： Tony Lin , Jih-Wen Chou , C. C. Hsue
IPC分类号： H01L21425
CPC分类号： H01L21/28518 , H01L21/26506 , H01L29/665
摘要： A method for forming an amorphous silicon layer over the terminals of a MOS transistor. The method includes the steps of forming a mask layer having an opening that exposes the gate polysilicon layer over the MOS transistor. Next, using the mask layer as a mask, an inactive ion implant operation is carried out such that inactive ions are implanted into the gate polysilicon layer. Thereafter, again using the mask layer as a mask, a first heavy bombarding operation is carried out, implanting ions locally. Finally, the mask layer is removed and then a second heavy bombarding operation is carried out, implanting ions globally.
摘要翻译：一种用于在MOS晶体管的端子上形成非晶硅层的方法。该方法包括以下步骤：形成具有在MOS晶体管上暴露栅极多晶硅层的开口的掩模层。接下来，使用掩模层作为掩模，执行非活性离子注入操作，使得非活性离子注入到栅极多晶硅层中。此后，再次使用掩模层作为掩模，进行第一次重轰击操作，局部注入离子。最后，去除掩模层，然后进行第二次重轰击操作，全局注入离子。

10. 发明授权

US06165857A Method for forming a transistor with selective epitaxial growth film 有权
标题翻译：用选择性外延生长膜形成晶体管的方法
公开(公告)号：US06165857A
公开(公告)日：2000-12-26
申请号：US469008
申请日：1999-12-21
申请人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
IPC分类号： H01L21/28 , H01L21/336 , H01L29/417
CPC分类号： H01L29/6659 , H01L21/28052 , H01L29/41775 , H01L29/665 , H01L29/6656 , H01L29/66628
摘要： A new improvement for selective epitaxial growth is disclosed. In one embodiment, the present invention provides a low power metal oxide semiconductor field effect transistor (MOSFET), which includes a substrate. Next, a gate oxide layer is formed on the substrate. Moreover, a polysilicon layer is deposited on the gate oxide layer. Patterning to etch the polysilicon layer and the gate oxide layer to define a gate. First ions are implanted into the substrate by using said gate as a hard mask. Sequentially, a liner oxide is covered over the entire exposed surface of the resulting structure. Moreover, a conformal first dielectric layer and second dielectric layer are deposited above the liner oxide in proper order. The second dielectric layer is etched back to form a dielectric spacer on sidewall of the first dielectric layer. Next, the first dielectric layer is etched until upper surface of the gate and a portion of the substrate are exposed, wherein a part of the second dielectric layer is also etched accompanying with etching a part of the first dielectric layer. Further, second ions are implanted into the exposed substrate to form a source/drain region. A conductive layer is selectively formed on said over the exposed gate and source/drain. Finally, a self-aligned silicide layer is formed over the conductive layer.
摘要翻译：公开了选择性外延生长的新改进。在一个实施例中，本发明提供一种包括衬底的低功率金属氧化物半导体场效应晶体管（MOSFET）。接着，在基板上形成栅极氧化层。此外，在栅极氧化物层上沉积多晶硅层。图案化以蚀刻多晶硅层和栅极氧化物层以限定栅极。通过使用所述栅极作为硬掩模将第一离子注入到衬底中。接下来，衬垫氧化物覆盖在所得结构的整个暴露表面上。此外，适形的第一介电层和第二介电层以适当的顺序沉积在衬垫氧化物的上方。回蚀第二电介质层以在第一电介质层的侧壁上形成电介质间隔物。接下来，蚀刻第一电介质层直到栅极的上表面和衬底的一部分被暴露，其中第二电介质层的一部分也被蚀刻，同时蚀刻第一介电层的一部分。此外，将第二离子注入暴露的衬底中以形成源/漏区。在暴露的栅极和源极/漏极上的选择性地形成导电层。最后，在导电层上形成自对准的硅化物层。

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