专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20070001303A1 INTEGRATED CIRCUIT SYSTEM USING DUAL DAMASCENE PROCESS 有权
标题翻译：集成电路系统使用双重DAMASCENE过程
公开(公告)号：US20070001303A1
公开(公告)日：2007-01-04
申请号：US11160624
申请日：2005-06-30
申请人： Yeow Kheng Lim , Chim Seng Seet , Tae Jong Lee , Liang-Choo Hsia , Kin Leong Pey
发明人： Yeow Kheng Lim , Chim Seng Seet , Tae Jong Lee , Liang-Choo Hsia , Kin Leong Pey
IPC分类号： H01L23/52
CPC分类号： H01L21/76831 , H01L21/76814 , H01L21/76844 , H01L21/76846
摘要： An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.
摘要翻译：集成电路系统包括提供其上设置有半导体器件的半导体衬底。第一电介质层形成在半导体衬底之上，并且第一导体芯形成在第一电介质层中。在第一导体芯上形成停止层。在停止层上形成第二电介质层。在第二电介质层中形成沟道和通孔。第二介质层中的通道和通孔被湿清洗。沉积阻挡金属层以在第二介电层中对通道和通孔进行排列。从电介质层中的通孔的底部选择性地蚀刻阻挡金属层，并且在阻挡金属层上方形成第二导体芯以填充第二通道和通孔，以将第二导体芯连接到第一导体芯。

22. 发明授权

US06849928B2 Dual silicon-on-insulator device wafer die 失效
标题翻译：双硅绝缘体上硅器件芯片
公开(公告)号：US06849928B2
公开(公告)日：2005-02-01
申请号：US10327309
申请日：2002-12-19
申请人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
发明人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
IPC分类号： H01L21/762 , H01L23/28
CPC分类号： H01L21/76264 , H01L21/76278 , H01L21/76281 , H01L21/76283 , H01L2924/0002 , Y10S438/967 , H01L2924/00
摘要： A silicon-on-insulator semiconductor device is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.
摘要翻译：提供一种绝缘体上半导体器件，其中单个晶片管芯在绝缘体层上包含晶体管以形成完全耗尽的绝缘体上硅器件，并且在半导体晶片上的绝缘体结构上形成半导体岛中的晶体管形成部分耗尽的绝缘体上硅器件。

23. 发明授权

US08766454B2 Integrated circuit with self-aligned line and via 有权
标题翻译：具有自对准线和通孔的集成电路
公开(公告)号：US08766454B2
公开(公告)日：2014-07-01
申请号：US11466018
申请日：2006-08-21
申请人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh
发明人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh
IPC分类号： H01L23/48 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.
摘要翻译：提供一种集成电路，其具有形成在其上的第一电介质层的基极。在第一电介质层上形成第二电介质层。第三电介质层形成在第二电介质层上的间隔开的条带中。第一沟槽开口通过第三和第二电介质层形成在第三介电层间隔开的条之间。第二沟槽开口与通过第一介电层的第一沟槽开口连续地形成在第三介电层的间隔开的条之间。沟槽开口中的导体金属形成自对准沟槽互连。

24. 发明授权

US06380084B1 Method to form high performance copper damascene interconnects by de-coupling via and metal line filling 有权
标题翻译：通过去耦合通孔和金属线填充形成高性能铜镶嵌互连的方法
公开(公告)号：US06380084B1
公开(公告)日：2002-04-30
申请号：US09678621
申请日：2000-10-02
申请人： Yeow Kheng Lim , Alex See , Cher Liang Cha , Subhash Gupta , Wang Ling Goh , Man Siu Tse
发明人： Yeow Kheng Lim , Alex See , Cher Liang Cha , Subhash Gupta , Wang Ling Goh , Man Siu Tse
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/32051 , H01L21/76802 , H01L21/76849 , H01L21/7685 , H01L21/76877 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method to form robust dual damascene interconnects by decoupling via and connective line trench filling has been achieved. A first dielectric layer is deposited overlying a silicon nitride layer. A shielding layer is deposited. The shielding layer, the first dielectric layer, and the silicon nitride layer are patterned to form via trenches. A first barrier layer is deposited to line the trenches. The via trenches are filled with a first copper layer by a single deposition or by depositing a seed layer and then electroless or electrochemical plating. The first copper layer is polished down to complete the vias. A second barrier layer is deposited. The second barrier layer is patterned to form via caps. A second dielectric layer is deposited. A capping layer is deposited. The capping layer and the second dielectric layer are patterned to form connective line trenches that expose a part of the via caps. A third barrier layer is deposited to line the connective line trenches. The third barrier layer and the via caps are etched to form trench barrier sidewall spacers and to expose the vias. The connective line trenches are filled with a second copper layer by a single deposition, by a first deposition of a seed layer followed by plating, or by plating using the via as the seed layer. The second copper layer is polished down.
摘要翻译：已经实现了通过解耦通孔和连接线沟槽填充形成鲁棒的双镶嵌互连的方法。沉积在氮化硅层上的第一介电层。屏蔽层被沉积。将屏蔽层，第一介电层和氮化硅层图案化以形成通孔沟槽。沉积第一势垒层以对沟槽进行排列。通过单个沉积或通过沉积种子层然后进行无电镀或电化学电镀，将通孔沟槽填充有第一铜层。第一个铜层被抛光以完成通孔。沉积第二阻挡层。图案化第二阻挡层以形成通孔。沉积第二介电层。沉积覆盖层。图案化覆盖层和第二介电层以形成连接线沟槽，其暴露通孔盖的一部分。沉积第三阻挡层以对连接线沟槽进行排列。蚀刻第三阻挡层和通孔盖以形成沟槽阻挡侧壁间隔件并露出通孔。连接线沟槽通过单次沉积，通过第一次沉积种子层，然后电镀，或通过使用通孔作为种子层进行电镀，填充第二铜层。第二个铜层被抛光。

25. 发明授权

US07790617B2 Formation of metal silicide layer over copper interconnect for reliability enhancement 有权
标题翻译：在铜互连上形成金属硅化物层，以提高可靠性
公开(公告)号：US07790617B2
公开(公告)日：2010-09-07
申请号：US11273108
申请日：2005-11-12
申请人： Yeow Kheng Lim , Wei Lu , Liang Choo Hsia , Jyoti Gupta , Chim Seng Seet , Hao Zhang
发明人： Yeow Kheng Lim , Wei Lu , Liang Choo Hsia , Jyoti Gupta , Chim Seng Seet , Hao Zhang
IPC分类号： H01L21/441
CPC分类号： H01L21/76831 , H01L21/2855 , H01L21/76849 , H01L21/76877
摘要： A method of fabrication of a sputtered metal silicide layer over a copper interconnect. We form a dielectric layer over a conductive layer. We form an interconnect opening in the dielectric layer. We form a copper layer at least filling the interconnect opening. We planarize the copper layer to form a copper interconnect in the interconnect opening. The copper interconnect is over polished to form a depression. We form metal silicide layer over the copper interconnect using a low temperature sputtering process. We can form a cap layer over the metal silicide layer.
摘要翻译：一种在铜互连上制造溅射金属硅化物层的方法。我们在导电层上形成介电层。我们在电介质层中形成互连开口。我们形成至少填充互连开口的铜层。我们平面化铜层以在互连开口中形成铜互连。铜互连件被抛光以形成凹陷。我们使用低温溅射工艺在铜互连上形成金属硅化物层。我们可以在金属硅化物层上形成覆盖层。

26. 发明授权

US06518133B1 Method for fabricating a small dimensional gate with elevated source/drain structures 有权
标题翻译：用于制造具有升高的源极/漏极结构的小尺寸栅极的方法
公开(公告)号：US06518133B1
公开(公告)日：2003-02-11
申请号：US10128967
申请日：2002-04-24
申请人： Alex See , Yeow Kheng Lim , Cher Liang Randall Cha
发明人： Alex See , Yeow Kheng Lim , Cher Liang Randall Cha
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/76877 , H01L29/42376 , H01L29/6653 , H01L29/66553 , H01L29/6659 , H01L29/7833
摘要： A method of manufacturing a transistor with a small self aligned gate and self aligned elevated source/drain regions. A first insulating layer is formed over a substrate. A first opening is formed in the first insulating layer to expose the substrate. We form a gate dielectric layer over the substrate in the first opening. Next, first spacers are formed on the sidewalls of the first insulating layer. A gate layer is formed over the first insulating layer, the first spacers, and the gate dielectric layer. We planarize the gate layer to form a gate electrode. The first spacers are removed to form LDD openings. Next, we form lightly doped source/drain regions in the substrate in the LDD openings. Subsequently, second spacers are formed on the sidewalls of the first insulating layer and on the sidewalls of the gate electrode to form S/D openings. Source/drain regions are formed in the substrate in the S/D openings. Next, we form a conductive layer over the substrate at least partially filling the S/D openings. The conductive layer is planarized to form elevated source/drain structures.
摘要翻译：一种制造具有小的自对准栅极和自对准升高的源极/漏极区域的晶体管的方法。第一绝缘层形成在衬底上。在第一绝缘层中形成第一开口以露出衬底。我们在第一开口中在衬底上形成栅介质层。接下来，在第一绝缘层的侧壁上形成第一间隔物。在第一绝缘层，第一间隔物和栅极电介质层上形成栅极层。我们平面化栅极层以形成栅电极。去除第一间隔物以形成LDD开口。接下来，我们在LDD开口中的衬底中形成轻掺杂的源极/漏极区域。随后，在第一绝缘层的侧壁和栅电极的侧壁上形成第二间隔物以形成S / D开口。源极/漏极区域形成在S / D开口中的衬底中。接下来，我们在衬底上形成至少部分填充S / D开口的导电层。导电层被平坦化以形成升高的源极/漏极结构。

27. 发明授权

US07119010B2 Integrated circuit with self-aligned line and via and manufacturing method therefor 有权
公开(公告)号：US07119010B2
公开(公告)日：2006-10-10
申请号：US10128875
申请日：2002-04-23
申请人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh
发明人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

28. 发明授权

US06780691B2 Method to fabricate elevated source/drain transistor with large area for silicidation 失效
公开(公告)号：US06780691B2
公开(公告)日：2004-08-24
申请号：US10222410
申请日：2002-08-16
申请人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex Kai Hung See , Jia Zhen Zheng
发明人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex Kai Hung See , Jia Zhen Zheng
IPC分类号： H01L2100
CPC分类号： H01L29/66583 , H01L21/28123 , H01L21/76235 , H01L21/823814 , H01L29/41783 , H01L29/665
摘要： A method for forming a transistor having an elevated source/drain structure is described. A gate electrode is formed overlying a substrate and isolated from the substrate by a gate dielectric layer. Isolation regions are formed in and on the substrate wherein the isolation regions have a stepped profile wherein an upper portion of the isolation regions partly overlaps and is offset from a lower portion of the isolation regions in the direction away from the gate electrode. Ions are implanted into the substrate between the gate electrode and the isolation regions to form source/drain extensions. Dielectric spacers are formed on sidewalls of the gate electrode and the isolation regions. A conductive layer is deposited overlying the substrate, the gate electrode, and the isolation regions and planarized to leave the conductive layer adjacent to the gate electrode and separated from the gate electrode by the dielectric spacers wherein the conductive layer forms elevated source/drain junctions and wherein the elevated source/drain junctions completely overlie the source/drain extensions and wherein an upper portion of the elevated source/drain junctions extends into the stepped portion of the isolation regions thereby completing formation of a MOSFET having an elevated source/drain structure.

29. 发明授权

US06472697B2 Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application 有权
公开(公告)号：US06472697B2
公开(公告)日：2002-10-29
申请号：US10140574
申请日：2002-05-08
申请人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh , Victor Seng Keong Lim
发明人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh , Victor Seng Keong Lim
IPC分类号： H01L2710
CPC分类号： H01L21/76838 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.

30. 发明授权

US06399471B1 Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application 失效
公开(公告)号：US06399471B1
公开(公告)日：2002-06-04
申请号：US09783379
申请日：2001-02-15
申请人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh , Victor Seng Keong Lim
发明人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh , Victor Seng Keong Lim
IPC分类号： H01L2144
CPC分类号： H01L21/76838 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式