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1. 发明授权

US06780691B2 Method to fabricate elevated source/drain transistor with large area for silicidation 失效
公开(公告)号：US06780691B2
公开(公告)日：2004-08-24
申请号：US10222410
申请日：2002-08-16
申请人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex Kai Hung See , Jia Zhen Zheng
发明人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex Kai Hung See , Jia Zhen Zheng
IPC分类号： H01L2100
CPC分类号： H01L29/66583 , H01L21/28123 , H01L21/76235 , H01L21/823814 , H01L29/41783 , H01L29/665
摘要： A method for forming a transistor having an elevated source/drain structure is described. A gate electrode is formed overlying a substrate and isolated from the substrate by a gate dielectric layer. Isolation regions are formed in and on the substrate wherein the isolation regions have a stepped profile wherein an upper portion of the isolation regions partly overlaps and is offset from a lower portion of the isolation regions in the direction away from the gate electrode. Ions are implanted into the substrate between the gate electrode and the isolation regions to form source/drain extensions. Dielectric spacers are formed on sidewalls of the gate electrode and the isolation regions. A conductive layer is deposited overlying the substrate, the gate electrode, and the isolation regions and planarized to leave the conductive layer adjacent to the gate electrode and separated from the gate electrode by the dielectric spacers wherein the conductive layer forms elevated source/drain junctions and wherein the elevated source/drain junctions completely overlie the source/drain extensions and wherein an upper portion of the elevated source/drain junctions extends into the stepped portion of the isolation regions thereby completing formation of a MOSFET having an elevated source/drain structure.

2. 发明申请

US20140008810A1 METHOD FOR FORMING THROUGH SILICON VIA WITH WAFER BACKSIDE PROTECTION 有权
标题翻译：通过硅片防止背面保护形成硅的方法
公开(公告)号：US20140008810A1
公开(公告)日：2014-01-09
申请号：US13542256
申请日：2012-07-05
申请人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
发明人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
IPC分类号： H01L21/306 , H01L23/48
CPC分类号： H01L23/481 , H01L21/02107 , H01L21/486 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/13009 , H01L2224/1357
摘要： Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.
摘要翻译：具有贯通硅通孔（TSV）的半导体器件不形成铜污染。实施例包括在硅衬底中暴露围绕TSV的底部的钝化层，在暴露的钝化层上方并在硅衬底的底表面上形成硅复合层，在硅复合层上形成硬掩模层，硅衬底的底表面，使用硬掩模层作为掩模去除围绕TSV的底部部分的硅复合层的一部分，再次暴露钝化层，以及将硬掩模层和再曝光的钝化层移除到暴露TSV底部的触点。

3. 发明授权

US08415236B2 Methods for reducing loading effects during film formation 有权
标题翻译：降低成膜时负荷效应的方法
公开(公告)号：US08415236B2
公开(公告)日：2013-04-09
申请号：US12648309
申请日：2009-12-29
申请人： Han Guan Chew , Jinping Liu , Alex Kai Hung See , Mei Sheng Zhou
发明人： Han Guan Chew , Jinping Liu , Alex Kai Hung See , Mei Sheng Zhou
IPC分类号： H01L21/20
CPC分类号： H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/823412 , H01L21/823418 , H01L29/7848
摘要： A method for fabricating a semiconductor device is provided. The method comprises selectively forming a first layer over a first and second exposed portions of a substrate. The first and second exposed portions are of different sizes and are located adjacent to a first and second active devices. During the first layer formation, a gas mixture comprising first and second source gases that function as growth components for forming the first layer and a reactant gas that functions as an etching component for controlling selectivity of the first layer growth is provided. The reactant gas is different from the first and second source gases and one of first and second source gases forms the first layer at a faster rate over the first exposed portion as compared to the second exposed portion and the other source gas exhibits an opposite behavior.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在衬底的第一和第二暴露部分上选择性地形成第一层。第一和第二暴露部分具有不同的尺寸并且位于第一和第二有源器件附近。在第一层形成期间，提供了包含用作形成第一层的生长组分的第一和第二源气体和用作控制第一层生长选择性的蚀刻组分的反应气体的气体混合物。反应物气体与第一和第二源气体不同，并且第一和第二源气体之一与第二暴露部分相比以较快的速率在第一暴露部分上形成第一层，而另一个源气体表现出相反的作用。

4. 发明授权

US08940637B2 Method for forming through silicon via with wafer backside protection 有权
标题翻译：通过硅晶片背面保护形成硅通孔的方法
公开(公告)号：US08940637B2
公开(公告)日：2015-01-27
申请号：US13542256
申请日：2012-07-05
申请人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
发明人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
IPC分类号： H01L21/44 , H01L21/768 , H01L21/48
CPC分类号： H01L23/481 , H01L21/02107 , H01L21/486 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/13009 , H01L2224/1357
摘要： Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.
摘要翻译：具有贯通硅通孔（TSV）的半导体器件不形成铜污染。实施例包括在硅衬底中暴露围绕TSV的底部的钝化层，在暴露的钝化层上方并在硅衬底的底表面上形成硅复合层，在硅复合层上形成硬掩模层，硅衬底的底表面，使用硬掩模层作为掩模去除围绕TSV的底部部分的硅复合层的一部分，再次暴露钝化层，以及将硬掩模层和再曝光的钝化层移除到暴露TSV底部的触点。

5. 发明授权

US08518775B2 Integration of eNVM, RMG, and HKMG modules 有权
标题翻译：集成eNVM，RMG和HKMG模块
公开(公告)号：US08518775B2
公开(公告)日：2013-08-27
申请号：US13251444
申请日：2011-10-03
申请人： Huang Liu , Alex Kai Hung See , Hai Cong , Zheng Zou
发明人： Huang Liu , Alex Kai Hung See , Hai Cong , Zheng Zou
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L21/823456 , H01L21/76229 , H01L21/76232 , H01L21/823462 , H01L21/823481 , H01L21/82385 , H01L21/823857 , H01L21/823878 , H01L27/11546 , H01L29/66545
摘要： A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.
摘要翻译：通过将嵌入式非易失性存储器（eNVM）与替代金属栅极（RMG）和高k /金属栅极（HKMG）模块集成来制造存储器件。实施例包括形成具有不同高度的上表面的两个基板部分，在具有下上表面的基板部分上形成非易失性栅极堆叠，以及在另一个基板部分上形成高压栅极堆叠和逻辑栅极堆叠。实施例包括非电压栅极堆叠的上表面，高压栅极堆叠以及基本共面的逻辑门叠层。

6. 发明申请

US20130082318A1 INTEGRATION OF eNVM, RMG, AND HKMG MODULES 有权
标题翻译：整合eNVM，RMG和HKMG模块
公开(公告)号：US20130082318A1
公开(公告)日：2013-04-04
申请号：US13251444
申请日：2011-10-03
申请人： Huang Liu , Alex Kai Hung See , Hai Cong , Zheng Zou
发明人： Huang Liu , Alex Kai Hung See , Hai Cong , Zheng Zou
IPC分类号： H01L29/792 , H01L21/762
CPC分类号： H01L21/823456 , H01L21/76229 , H01L21/76232 , H01L21/823462 , H01L21/823481 , H01L21/82385 , H01L21/823857 , H01L21/823878 , H01L27/11546 , H01L29/66545
摘要： A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.
摘要翻译：通过将嵌入式非易失性存储器（eNVM）与替代金属栅极（RMG）和高k /金属栅极（HKMG）模块集成来制造存储器件。实施例包括形成具有不同高度的上表面的两个基板部分，在具有下上表面的基板部分上形成非易失性栅极堆叠，以及在另一个基板部分上形成高压栅极堆叠和逻辑栅极堆叠。实施例包括非电压栅极堆叠的上表面，高压栅极堆叠以及基本共面的逻辑门叠层。

7. 发明授权

US09034720B2 Litho scanner alignment signal improvement 有权
标题翻译： Litho扫描仪对准信号改善
公开(公告)号：US09034720B2
公开(公告)日：2015-05-19
申请号：US13588018
申请日：2012-08-17
申请人： Hui Liu , Wen Zhan Zhou , Zheng Zou , Qun Ying Lin , Alex Kai Hung See
发明人： Hui Liu , Wen Zhan Zhou , Zheng Zou , Qun Ying Lin , Alex Kai Hung See
IPC分类号： H01L21/76 , G02B6/136 , G03F7/20 , G02B6/124
CPC分类号： G02B6/136 , G02B6/124 , G03F7/70633
摘要： A method and a device are provided for diffracting incident light from a lithographic scanner in an IC process flow. Embodiments include forming a diffraction grating in a first layer on a semiconductor substrate; and forming a plurality of lithographic alignment marks in a second layer, overlying the first layer, wherein the diffraction grating has a width and a length greater than or equal to a width and length, respectively, of the plurality of lithographic alignment marks.
摘要翻译：提供了一种用于在IC工艺流程中衍射来自光刻扫描仪的入射光的方法和装置。实施例包括在半导体衬底上的第一层中形成衍射光栅; 以及在覆盖所述第一层的第二层中形成多个平版印刷对准标记，其中所述衍射光栅的宽度和长度分别大于或等于所述多个平版印刷对准标记的宽度和长度。

8. 发明申请

US20140050439A1 LITHO SCANNER ALIGNMENT SIGNAL IMPROVEMENT 有权
标题翻译： LITHO扫描仪对准信号改进
公开(公告)号：US20140050439A1
公开(公告)日：2014-02-20
申请号：US13588018
申请日：2012-08-17
申请人： Hui LIU , Wen Zhan Zhou , Zheng Zou , Qun Ying Lin , Alex Kai Hung See
发明人： Hui LIU , Wen Zhan Zhou , Zheng Zou , Qun Ying Lin , Alex Kai Hung See
IPC分类号： G02B6/12 , H01L33/10
CPC分类号： G02B6/136 , G02B6/124 , G03F7/70633
摘要： A method and a device are provided for diffracting incident light from a lithographic scanner in an IC process flow. Embodiments include forming a diffraction grating in a first layer on a semiconductor substrate; and forming a plurality of lithographic alignment marks in a second layer, overlying the first layer, wherein the diffraction grating has a width and a length greater than or equal to a width and length, respectively, of the plurality of lithographic alignment marks.
摘要翻译：提供了一种用于在IC工艺流程中衍射来自光刻扫描仪的入射光的方法和装置。实施例包括在半导体衬底上的第一层中形成衍射光栅; 以及在覆盖所述第一层的第二层中形成多个平版印刷对准标记，其中所述衍射光栅的宽度和长度分别大于或等于所述多个平版印刷对准标记的宽度和长度。

9. 发明申请

US20120273949A1 METHOD OF FORMING OXIDE ENCAPSULATED CONDUCTIVE FEATURES 审中-公开
标题翻译：形成氧化物导电性能的方法
公开(公告)号：US20120273949A1
公开(公告)日：2012-11-01
申请号：US13095140
申请日：2011-04-27
申请人： Huang Liu , Chim Seng Seet , Alex Kai Hung See
发明人： Huang Liu , Chim Seng Seet , Alex Kai Hung See
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76831 , H01L21/76834 , H01L21/76843 , H01L21/76856 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices are formed with a Cu or Cu alloy interconnect encapsulated by a substantially uniform MnO or Al2O3 layer. Embodiments include forming an opening having side surfaces and a bottom surface in a dielectric layer, forming a barrier layer on the side surfaces and the bottom surface of the opening and on an upper surface of the dielectric layer, treating the barrier layer with an oxygen plasma to form dangling oxygen atoms on the barrier layer, depositing a seed layer on the barrier layer, and filling the opening with Cu or a Cu alloy.
摘要翻译：半导体器件由具有基本上均匀的MnO或Al 2 O 3层封装的Cu或Cu合金互连形成。实施例包括在电介质层中形成具有侧表面和底表面的开口，在开口的侧表面和底表面以及电介质层的上表面上形成阻挡层，用氧等离子体处理阻挡层在阻挡层上形成悬浮的氧原子，在阻挡层上沉积种子层，并用Cu或Cu合金填充开口。

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