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21. 发明申请

US20100059809A1 NON-VOLATILE MEMORY AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20100059809A1
公开(公告)日：2010-03-11
申请号：US12268593
申请日：2008-11-11
申请人： Chi-Pin Lu , Jung-Yu Hsieh , Hsing-Ju Lin
发明人： Chi-Pin Lu , Jung-Yu Hsieh , Hsing-Ju Lin
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L29/40114 , H01L29/40117 , H01L29/7881
摘要： A method of fabricating a non-volatile memory is provided. First, a bottom oxide layer is formed on a substrate. Thereafter, a silicon-rich nitride layer is formed on the bottom oxide layer by using NH3 and SiH2Cl2 or SiH4, wherein the thickness of the silicon-rich nitride layer is less than about 40 Å, and the gas flow ratio of NH3 to SiH2Cl2 or SiH4 is about 0.2-0.5. Afterwards, a top oxide layer is formed on the silicon-rich nitride layer. Further, a gate is formed on the top oxide layer. Two doped regions are then formed in the substrate beside the gate.
摘要翻译：提供了一种制造非易失性存储器的方法。首先，在基板上形成底部氧化物层。此后，通过使用NH 3和SiH 2 Cl 2或SiH 4在底部氧化物层上形成富含硅的氮化物层，其中富硅氮化物层的厚度小于约40，NH 3与SiH 2 Cl 2的气体流量比 SiH4约为0.2-0.5。之后，在富硅氮化物层上形成顶部氧化物层。此外，在顶部氧化物层上形成栅极。然后在栅极旁边的衬底中形成两个掺杂区域。

22. 发明授权

US08581322B2 Nonvolatile memory device and method for making the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08581322B2
公开(公告)日：2013-11-12
申请号：US13170618
申请日：2011-06-28
申请人： Chi-Pin Lu , Jung-Yu Hsieh , Ling-Wuu Yang
发明人： Chi-Pin Lu , Jung-Yu Hsieh , Ling-Wuu Yang
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521
摘要： A method for making a nonvolatile memory device includes the following steps. A conductive structure is formed, wherein the conductive structure has a first top portion. The first top portion is converted into a second top portion having a domed surface.
摘要翻译：一种制造非易失性存储器件的方法包括以下步骤。形成导电结构，其中导电结构具有第一顶部部分。第一顶部部分被转换成具有圆顶表面的第二顶部部分。

23. 发明申请

US20070298583A1 METHOD FOR FORMING A SHALLOW TRENCH ISOLATION REGION 审中-公开
标题翻译：形成浅层分离区的方法
公开(公告)号：US20070298583A1
公开(公告)日：2007-12-27
申请号：US11426650
申请日：2006-06-27
申请人： Chia-Wei Wu , Chen-Wei Liao , Jung-Yu Hsieh , Ling-Wuu Yang , Chin-Ta Su , Chi-Tung Huang
发明人： Chia-Wei Wu , Chen-Wei Liao , Jung-Yu Hsieh , Ling-Wuu Yang , Chin-Ta Su , Chi-Tung Huang
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A method for forming a shallow trench isolation region (STI) is disclosed. The method comprises the steps of sequentially forming a pad oxide layer and a nitride silicon layer over a provided substrate. Next, the pad oxide layer, the nitride silicon layer, and the substrate are partially etched to form a trench. An oxide liner and a nitride liner are then formed in the trench. Subsequently, a two-stage high-density plasma chemical vapor deposition process is performed to form a shallow trench isolation region.
摘要翻译：公开了一种用于形成浅沟槽隔离区域（STI）的方法。该方法包括以下步骤：在所提供的衬底上顺序地形成衬垫氧化物层和氮化硅层。接下来，对衬垫氧化物层，氮化物硅层和衬底进行部分蚀刻以形成沟槽。然后在沟槽中形成氧化物衬垫和氮化物衬垫。随后，进行两级高密度等离子体化学气相沉积工艺以形成浅沟槽隔离区域。

24. 发明申请

US20060148197A1 Method for forming shallow trench isolation with rounded corners by using a clean process 审中-公开
标题翻译：通过使用清洁工艺形成具有圆角的浅沟槽隔离的方法
公开(公告)号：US20060148197A1
公开(公告)日：2006-07-06
申请号：US11134372
申请日：2005-05-23
申请人： Chia-Wei Wu , Cheng-Shun Chen , Jung-Yu Hsieh , Ling Yang
发明人： Chia-Wei Wu , Cheng-Shun Chen , Jung-Yu Hsieh , Ling Yang
IPC分类号： H01L21/76 , H01L21/302
CPC分类号： H01L21/30608 , H01L21/76232
摘要： In a method for forming STI in a silicon substrate having a pad oxide over the substrate, a hard mask is formed over the pad oxide, the hard mask and the pad oxide are patterned to form an opening, the silicon substrate is etched through the opening to form a trench, a liner oxide is formed over the trench, an STI insulator is formed in the trench, and the hard mask and the pad oxide are removed. Before the formation of the liner oxide, a clean process is performed that comprises applying silicon-consuming solution to round the top corners of the trench.
摘要翻译：在用于在衬底上具有衬垫氧化物的硅衬底中形成STI的方法中，在衬垫氧化物上方形成硬掩模，对硬掩模和衬垫氧化物进行构图以形成开口，通过开口蚀刻硅衬底为了形成沟槽，在沟槽上形成衬垫氧化物，在沟槽中形成STI绝缘体，并且去除硬掩模和衬垫氧化物。在形成衬垫氧化物之前，执行清洁工艺，其包括将消耗硅消耗溶液施加到沟槽的顶角四周。

25. 发明申请

US20060040446A1 Method for manufacturing interpoly dielectric 有权
公开(公告)号：US20060040446A1
公开(公告)日：2006-02-23
申请号：US10919921
申请日：2004-08-17
申请人： Jung-Yu Hsieh
发明人： Jung-Yu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/513
摘要： Roughly described, a floating gate memory cell is fabricated by forming an oxide-nitride dielectric layer above a floating gate of the memory cell and in an oxide growth region not above a floating gate. The nitride layer is removed in the oxide growth region using a mask that protects the nitride layer above the floating gate, and then the bottom oxide layer is removed in the oxide growth region using a wet etch that does not affect the nitride remaining above the floating gate. First and second oxide layers are then formed both above the floating gate and in the oxide growth region, to act as the top layer of ONO above the floating gate and as the gate oxide in the oxide growth region. One of the first and second oxide layers is formed using in-situ steam generation.

26. 发明授权

US08106483B2 Wafer with improved intrinsic gettering ability 失效
标题翻译：晶圆具有改善的内在吸气能力
公开(公告)号：US08106483B2
公开(公告)日：2012-01-31
申请号：US13074780
申请日：2011-03-29
申请人： Chun-Ling Chiang , Jung-Yu Hsieh , Ling-Wu Yang
发明人： Chun-Ling Chiang , Jung-Yu Hsieh , Ling-Wu Yang
IPC分类号： H01L29/30 , H01L29/207 , H01L29/227 , H01L29/167
CPC分类号： H01L21/3225
摘要： An integrated circuit with improved intrinsic gettering ability is described, having a bulk micro-defect (BMD) density of 3.85×105-3.38×109/cm3 through first and second annealing steps. The first annealing step is performed at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. The second annealing step is performed at a second temperature higher than the first temperature in the atmosphere.
摘要翻译：描述了具有改善的内在吸气能力的集成电路，通过第一和第二退火步骤具有3.85×10 5 -3.38×10 9 / cm 3的体积微缺陷（BMD）密度。第一退火步骤在包含氧气和氮气中的至少一种的气氛中的第一温度下进行。第二退火步骤在高于大气中的第一温度的第二温度下进行。

27. 发明申请

US20100178758A1 METHODS FOR FABRICATING DIELECTRIC LAYER AND NON-VOLATILE MEMORY 审中-公开
标题翻译：用于制造介电层和非易失性存储器的方法
公开(公告)号：US20100178758A1
公开(公告)日：2010-07-15
申请号：US12354602
申请日：2009-01-15
申请人： Jeng-Hwa Liao , Jung-Yu Hsieh , Ling-Wu Yang
发明人： Jeng-Hwa Liao , Jung-Yu Hsieh , Ling-Wu Yang
IPC分类号： H01L21/443 , H01L21/28
CPC分类号： H01L21/28202 , H01L21/0214 , H01L21/02211 , H01L21/02271 , H01L21/3145 , H01L29/40117
摘要： The method for fabricating the dielectric layer of the present invention is described as follows. A substrate is provided in a chamber, wherein the chamber is a single-wafer LPCVD chamber. A silicon source gas, an oxidation source gas and a nitridation source gas are then introduced into the chamber, wherein a volumetric flow rate ratio of the oxidation source gas to a total amount of the oxidation source gas and the nitridation source gas is varied within a range of 0.0245 to 0.375. Afterwards, the dielectric layer with a dielectric constant within a range of 4.8 to 7.6 is formed on the substrate.
摘要翻译：本发明的电介质层的制造方法如下所述。衬底设置在腔室中，其中腔室是单晶片LPCVD室。然后将硅源气体，氧化源气体和氮化源气体引入室中，其中氧化源气体与氧化源气体和氮化源气体的总量的体积流量比在范围为0.0245至0.375。之后，在基板上形成介电常数为4.8〜7.6的介质层。

28. 发明授权

US07118968B2 Method for manufacturing interpoly dielectric 有权
标题翻译：多聚电介质的制造方法
公开(公告)号：US07118968B2
公开(公告)日：2006-10-10
申请号：US10919921
申请日：2004-08-17
申请人： Jung-Yu Hsieh
发明人： Jung-Yu Hsieh
IPC分类号： H01L21/8247
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/513
摘要： Roughly described, a floating gate memory cell is fabricated by forming an oxide-nitride dielectric layer above a floating gate of the memory cell and in an oxide growth region not above a floating gate. The nitride layer is removed in the oxide growth region using a mask that protects the nitride layer above the floating gate, and then the bottom oxide layer is removed in the oxide growth region using a wet etch that does not affect the nitride remaining above the floating gate. First and second oxide layers are then formed both above the floating gate and in the oxide growth region, to act as the top layer of ONO above the floating gate and as the gate oxide in the oxide growth region. One of the first and second oxide layers is formed using in-situ steam generation.
摘要翻译：粗略地描述，通过在存储器单元的浮动栅极上方和不在浮动栅极上方的氧化物生长区域中形成氧化物 - 氮化物电介质层来制造浮动栅极存储单元。在氧化物生长区域中使用保护氮化物层的掩模在氧化物生长区域中去除氮化物层，然后在氧化物生长区域中去除底部氧化物层，使用湿蚀刻，该蚀刻不会影响浮在浮动栅极上方的氮化物门。然后在浮置栅极上方和氧化物生长区域中形成第一和第二氧化物层，以在浮栅上方作为ONO的顶层，并且作为氧化物生长区域中的栅极氧化物。第一和第二氧化物层中的一个是使用原位蒸汽产生形成的。

29. 发明授权

US06536130B1 Overlay mark for concurrently monitoring alignment accuracy, focus, leveling and astigmatism and method of application thereof 有权
标题翻译：叠加标记，用于同时监测对准精度，对焦，调平和散光及其应用方法
公开(公告)号：US06536130B1
公开(公告)日：2003-03-25
申请号：US09998286
申请日：2001-11-30
申请人： Te-Hung Wu , Jung-Yu Hsieh , Hsiu-Man Chang
发明人： Te-Hung Wu , Jung-Yu Hsieh , Hsiu-Man Chang
IPC分类号： G01B1100
CPC分类号： G03F7/70633 , G03F7/70641 , Y10S414/136
摘要： An overlay mark for concurrently monitoring alignment accuracy, focus, leveling and astigmatism and a method of application thereof are disclosed. The overlay mark comprises four inner bars and four outer bars formed at the corners of exposure areas. The inner bar has a sawtooth area and a bar-shaped area, and the outer bar is a fore-layer etched pattern. Both the inner bars and the outer bars are formed into rectangles, and each bar is one side of a rectangle and none of the sides are connected. The sawtooth areas of the inner bars disposed on opposite sides are located at a same position. The rectangle formed by the outer bars encloses the rectangle formed by the inner bars. During the monitoring process, a testing beam scans across a scan area being divided into two areas, i.e., one being the outer bars and the sawtooth area of the inner bars, and the other one being the outer bars and the bar-shaped area of the inner bars.
摘要翻译：公开了一种用于同时监视对准精度，对焦，调平和散光的重叠标记及其应用方法。覆盖标记包括形成在曝光区域的角部的四个内部条和四个外部条。内侧杆具有锯齿形区域和棒状区域，外侧杆是前层蚀刻图案。内杆和外杆都形成矩形，并且每个杆是矩形的一侧，并且没有一个侧面连接。设置在相对侧的内侧杆的锯齿区域位于相同位置。由外杆形成的矩形包围由内条形成的矩形。在监视过程中，测试光束扫描扫描区域被划分为两个区域，即一个是内部条的外部条和锯齿形区域，另一个是外部条和条形区域内条。

30. 发明授权

US07939432B2 Method of improving intrinsic gettering ability of wafer 有权
标题翻译：提高晶片内在吸气能力的方法
公开(公告)号：US07939432B2
公开(公告)日：2011-05-10
申请号：US12334829
申请日：2008-12-15
申请人： Chun-Ling Chiang , Jung-Yu Hsieh , Ling-Wu Yang
发明人： Chun-Ling Chiang , Jung-Yu Hsieh , Ling-Wu Yang
IPC分类号： H01L21/322 , H01L21/335 , H01L21/8232
CPC分类号： H01L21/3225
摘要： A method of improving the intrinsic gettering ability of a wafer is described. A first annealing step is performed to the wafer at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. A second annealing step is performed to the wafer, at a second temperature higher than the first temperature, in the atmosphere.
摘要翻译：描述了提高晶片的固有吸气能力的方法。在包含氧气和氮气中的至少一种的气氛中的第一温度下对晶片进行第一退火步骤。在大气中在高于第一温度的第二温度下对晶片进行第二退火步骤。

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