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21. 发明申请

US20070284659A1 METHOD OF FORMING HIGH VOLTAGE N-LDMOS TRANSISTORS HAVING SHALLOW TRENCH ISOLATION REGION WITH DRAIN EXTENSIONS 审中-公开
标题翻译：形成具有泄漏扩展的浅层分离区域的高电压N-LDMOS晶体管的方法
公开(公告)号：US20070284659A1
公开(公告)日：2007-12-13
申请号：US11844573
申请日：2007-08-24
申请人： Wagdi Abadeer , Jeffrey Brown , Robert Gauthier , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Robert Gauthier , Jed Rankin , William Tonti
IPC分类号： H01L29/78
CPC分类号： H01L29/0878 , H01L21/26586 , H01L21/266 , H01L29/0653 , H01L29/086 , H01L29/42368 , H01L29/66689 , H01L29/7816
摘要： A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.
摘要翻译：公开了一种用于晶体管的方法和结构，该晶体管具有栅极，栅极下方的沟道区，沟道区一侧的源极区，与源极区沟道区相反侧的漏极区，浅沟槽在漏极区和沟道区之间的衬底中的隔离（STI）区，以及在STI区之下的漏极延伸。漏极延伸沿着STI区域的底部并沿着STI的边的一部分定位。沿着STI底部的漏极延伸部分可以包括不同于沿着STI侧面的漏极延伸部分的掺杂剂注入。沿着STI侧面的排水延伸部分从STI的底部延伸到部分沿着STI侧面的位置。 STI区域位于栅极的一部分之下。漏极延伸部在漏极区域和围绕STI的下周边的沟道区域之间提供导电路径。漏极区域比源极区域更靠近栅极定位。

22. 发明申请

US20050073354A1 VOLTAGE DIVIDER FOR INTEGRATED CIRCUITS 失效
标题翻译：用于集成电路的电压分压器
公开(公告)号：US20050073354A1
公开(公告)日：2005-04-07
申请号：US10605466
申请日：2003-10-01
申请人： Wagdi Abadeer , John Fifield , William Tonti
发明人： Wagdi Abadeer , John Fifield , William Tonti
IPC分类号： G11C5/14 , H01L27/08 , H01L27/088 , H02J1/00 , H02M3/00
CPC分类号： G11C5/147 , H01L27/0802 , H01L27/088 , H02M3/00
摘要： A voltage divider for integrated circuits that does not include the use of resistors. In one embodiment, voltage node VDD is connected with two n-type transistors, NFET1 and NFET2, which are connected in series. NFET 1 includes a source (12), a drain (14), a gate electrode (16) having a gate area A1 (not shown), and a p-substrate (18). NFET2 includes a source (20), a drain (22), a gate electrode (24) having a gate area A2 (not shown), and a p-substrate (26). Source (12) and drain (14) of NFET1 are coupled with gate electrode (24) of NFET2. The voltage difference between NFET1 and NFET2 has a linear function with VDD. As a result, voltage VDD may be divided between NFET1 and NFET2 by properly choosing the ratio between each of the respective transistor gate electrode areas, (A1) and (A2).
摘要翻译：用于集成电路的分压器，不包括使用电阻器。在一个实施例中，电压节点VDD与串联连接的两个n型晶体管NFET1和NFET2连接。 NFET 1包括源极（12），漏极（14），具有栅极区域A1（未示出）的栅电极（16）和p衬底（18）。 NFET2包括源极（20），漏极（22），具有栅极区域A2（未示出）的栅电极（24）和p衬底（26）。 NFET1的源极（12）和漏极（14）与NFET2的栅电极（24）耦合。 NFET1和NFET2之间的电压差与VDD具有线性关系。结果，通过适当地选择各个晶体管栅电极区域（A1）和（A2）之间的比率，可以在NFET1和NFET2之间划分电压VDD。

23. 发明申请

US20060171189A1 SRAM CELL USING TUNNEL CURRENT LOADING DEVICES 失效
标题翻译：使用隧道电流负载装置的SRAM单元
公开(公告)号：US20060171189A1
公开(公告)日：2006-08-03
申请号：US10906056
申请日：2005-02-01
申请人： Wagdi Abadeer , John Fifield , Harold Pilo
发明人： Wagdi Abadeer , John Fifield , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , G11C11/412
摘要： An SRAM cell with gate tunneling load devices. The SRAM cell uses PFET wordline transistors and NFET cross-coupled transistors. The PFET wordline transistors are fully conductive during read operations, thus a full voltage level is passed through the PFET to the high node of the cell from the bitline. Tunnel current load devices maintain the high node of the cell at full voltage level during standby state.
摘要翻译：具有栅极隧道负载装置的SRAM单元。 SRAM单元使用PFET字线晶体管和NFET交叉耦合晶体管。 PFET字线晶体管在读取操作期间是完全导电的，因此，整个电压电平从位线通过PFET到电池的高节点。隧道电流负载设备在待机状态下将电池的高节点保持在全电压电平。

24. 发明申请

US20070124538A1 POWER-EFFICIENT CACHE MEMORY SYSTEM AND METHOD THEREFOR 审中-公开
标题翻译：功率高效的高速缓存存储器系统及其方法
公开(公告)号：US20070124538A1
公开(公告)日：2007-05-31
申请号：US11164656
申请日：2005-11-30
申请人： Wagdi Abadeer , George Braceras , John Fifield , Harold Pilo
发明人： Wagdi Abadeer , George Braceras , John Fifield , Harold Pilo
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要： A cache memory system (200) having a cache memory (204) partitioned into a number of banks, or “ways” (204A, 204B). The memory system includes a power controller (244) that selectively powers up and down the ways depending upon which way contains the data being sought by each incoming address (232) coming into the memory system.
摘要翻译：具有划分为多个存储体的高速缓冲存储器（204）或“路径”（204A，204B）的高速缓冲存储器系统（200）。存储器系统包括功率控制器（244），功率控制器（244）根据包含正在进入存储器系统的每个输入地址（232）寻找的数据的方式选择性地向上和向下加电。

25. 发明授权

US07326987B2 Non-continuous encapsulation layer for MIM capacitor 有权
标题翻译： MIM电容器的非连续封装层
公开(公告)号：US07326987B2
公开(公告)日：2008-02-05
申请号：US10908491
申请日：2005-05-13
申请人： Wagdi Abadeer , Eric Adler , Zhong-Xiang He , Bradley Orner , Vidhya Ramachandran , Barbara A. Waterhouse , Michael Zierak
发明人： Wagdi Abadeer , Eric Adler , Zhong-Xiang He , Bradley Orner , Vidhya Ramachandran , Barbara A. Waterhouse , Michael Zierak
IPC分类号： H01L27/108
CPC分类号： H01L28/57
摘要： The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.
摘要翻译：本发明涉及形成在半导体衬底上的金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）。 FET形成在线路前端（FEOL）电平以下的MIM电容器下面，这些电容器形成在上部后端（BEOL）电平。选择性地形成绝缘体层以封装MIM电容器的至少顶板，以保护MIM电容器免受由于诸如反应离子蚀刻等工艺步骤的损害。通过在MIM电容器上选择性地形成绝缘体层，提供层间电介质层中的开口，使得可以发生氢和/或氘到FET的扩散。

26. 发明申请

US20060261835A1 METHOD AND APPARATUS FOR BURN-IN OPTIMIZATION 失效
标题翻译：用于烧结优化的方法和装置
公开(公告)号：US20060261835A1
公开(公告)日：2006-11-23
申请号：US10908620
申请日：2005-05-19
申请人： Wagdi Abadeer , Harold Pilo , Daryl Seitzer
发明人： Wagdi Abadeer , Harold Pilo , Daryl Seitzer
IPC分类号： G01R31/26
CPC分类号： G01R31/287 , G01R31/2874
摘要： The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.
摘要翻译：本发明提供一种用于优化集成电路的老化的方法和装置。该方法的一个实施例包括：执行集成电路的老化过程的第一部分; 在老化过程的第一部分期间监测集成电路的功耗; 增加老化温度，直到集成电路的功耗达到预定的最大功耗; 以及在增加的老化温度下执行集成电路的老化过程的后续部分。

27. 发明申请

US20060170487A1 A VOLTAGE REFERENCE CIRCUIT FOR ULTRA-THIN OXIDE TECHNOLOGY AND LOW VOLTAGE APPLICATIONS 审中-公开
标题翻译：一种用于超薄氧化物技术和低电压应用的电压参考电路
公开(公告)号：US20060170487A1
公开(公告)日：2006-08-03
申请号：US10906012
申请日：2005-01-31
申请人： Wagdi Abadeer , John Fifield
发明人： Wagdi Abadeer , John Fifield
IPC分类号： G05F1/10
CPC分类号： G05F3/16
摘要： A precision voltage reference for ultra-thin gate oxide process technologies is realized with a network of tunneling current circuit elements. A voltage difference is measured between selected nodes of one or more current paths of a voltage divider. The tunneling current circuit element may be implemented with any suitable device, such as a parallel plate capacitor or MOSFET. The physical properties of gate tunneling currents enable the voltage reference output to be largely independent of temperature. The circuit may be implemented for low voltage operations with input power supply values of 1.2 volts or less. The output voltage tolerance may be designed to be about ±25% or less of a power supply voltage tolerance. In addition, variations in gate oxide thickness account for a change of less than about ±2% in the voltage reference generator output.
摘要翻译：通过隧道电流电路元件网络实现了超薄栅氧化物工艺技术的精密电压基准。在分压器的一个或多个电流路径的选定节点之间测量电压差。隧道电流电路元件可以用任何合适的器件来实现，例如并联板电容器或MOSFET。栅极隧道电流的物理特性使电压参考输出在很大程度上与温度无关。该电路可以用于1.2V或更小的输入电源值的低电压操作。输出电压公差可以设计为电源电压容差的±25％以下。此外，栅极氧化物厚度的变化在电压基准发生器输出中的变化小于约±2％。

28. 发明申请

US20070085557A1 METHOD AND APPARATUS FOR BURN-IN OPTIMIZATION 失效
标题翻译：用于烧结优化的方法和装置
公开(公告)号：US20070085557A1
公开(公告)日：2007-04-19
申请号：US11538833
申请日：2006-10-05
申请人： Wagdi Abadeer , Harold Pilo , Daryl Seitzer
发明人： Wagdi Abadeer , Harold Pilo , Daryl Seitzer
IPC分类号： G01R31/26
CPC分类号： G01R31/287 , G01R31/2874
摘要： The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.
摘要翻译：本发明提供一种用于优化集成电路的老化的方法和装置。该方法的一个实施例包括：执行集成电路的老化过程的第一部分; 在老化过程的第一部分期间监测集成电路的功耗; 增加老化温度，直到集成电路的功耗达到预定的最大功耗; 以及在增加的老化温度下执行集成电路的老化过程的后续部分。

29. 发明申请

US20050189615A1 NON-CONTINUOUS ENCAPSULATION LAYER FOR MIM CAPACITOR 有权
标题翻译： MIM电容器的非连续封装层
公开(公告)号：US20050189615A1
公开(公告)日：2005-09-01
申请号：US10908491
申请日：2005-05-13
申请人： Wagdi Abadeer , Eric Adler , Zhong-Xiang He , Bradley Orner , Vidhya Ramachandran , Barbara Waterhouse , Michael Zierak
发明人： Wagdi Abadeer , Eric Adler , Zhong-Xiang He , Bradley Orner , Vidhya Ramachandran , Barbara Waterhouse , Michael Zierak
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/57
摘要： The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.
摘要翻译：本发明涉及形成在半导体衬底上的金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）。 FET形成在线路前端（FEOL）电平以下的MIM电容器下面，这些电容器形成在上部后端（BEOL）电平。选择性地形成绝缘体层以封装MIM电容器的至少顶板，以保护MIM电容器免受由于诸如反应离子蚀刻等工艺步骤的损害。通过在MIM电容器上选择性地形成绝缘体层，提供层间电介质层中的开口，使得可以发生氢和/或氘到FET的扩散。

30. 发明授权

US06714113B1 Inductor for integrated circuits 有权
标题翻译：集成电路电感
公开(公告)号：US06714113B1
公开(公告)日：2004-03-30
申请号：US09712369
申请日：2000-11-14
申请人： Wagdi Abadeer , Robert A. Groves , Patrick Hansen
发明人： Wagdi Abadeer , Robert A. Groves , Patrick Hansen
IPC分类号： H01F2728
CPC分类号： H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An inductor is integrated in VLSI and ULSI technology products for very high frequency applications. The inductor is in a microstrip transmission line configuration which can be designed in a form of straight line, spiral line or Meander line. The inductor is formed by shorting the microstrip center conductor to the lower level ground plane at one end of the transmission line. This results in an inductance which, for a given design of transmission line, and in a specified frequency range, is independent of frequency, within the operating design range. The microstrip transmission line provides an inductance which could be used on any type of substrate, with either low or high resistivity. The microstrip transmission line could utilize two or all of the metal wiring levels of the technology, allowing a wide range of inductance and quality factor design tradeoffs. An important feature in this trade-off is the ability to utilize lower (below the inductor) metal wiring levels, as well as lower silicon and polysilicon areas for other than inductor design purposes, without affecting the operation of the inductor. This is because of the isolation properties of this inductor system. By utilizing isolation layers with low relative dielectric constant, Further enhancements of the system are achieved. The inductance of this system is constant within 10% over a frequency range extending from about 8 GHz to about 35 GHz This inductor system allows the design to be optimized, through several parameters, to achieve the desired performance.
摘要翻译：电感器集成在VLSI和ULSI技术产品中，适用于非常高频率的应用。电感器处于微带传输线配置中，可以以直线，螺旋线或曲折线的形式设计。电感器通过在传输线的一端将微带中心导体短路到下层接地平面而形成。这导致对于给定的传输线设计并且在指定的频率范围内，在操作设计范围内的电感是独立于频率的。微带传输线提供可用于任何类型的基板的电感，具有低或高电阻率。微带传输线可以利用该技术的两个或所有金属布线级别，允许广泛的电感和品质因数设计权衡。这种折衷的一个重要特征是能够利用低于（电感）以下的金属布线水平，以及除了电感器设计目的之外的较低的硅和多晶硅区域，而不会影响电感器的工作。这是因为这个电感系统的隔离性能。通过利用具有低相对介电常数的隔离层，实现了系统的进一步增强。该系统的电感在从大约8 GHz到大约35 GHz的频率范围内恒定在10％以内。该电感系统允许通过几个参数优化设计以实现所需的性能。

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