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1. 发明申请

US20070124538A1 POWER-EFFICIENT CACHE MEMORY SYSTEM AND METHOD THEREFOR 审中-公开
标题翻译：功率高效的高速缓存存储器系统及其方法
公开(公告)号：US20070124538A1
公开(公告)日：2007-05-31
申请号：US11164656
申请日：2005-11-30
申请人： Wagdi Abadeer , George Braceras , John Fifield , Harold Pilo
发明人： Wagdi Abadeer , George Braceras , John Fifield , Harold Pilo
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要： A cache memory system (200) having a cache memory (204) partitioned into a number of banks, or “ways” (204A, 204B). The memory system includes a power controller (244) that selectively powers up and down the ways depending upon which way contains the data being sought by each incoming address (232) coming into the memory system.
摘要翻译：具有划分为多个存储体的高速缓冲存储器（204）或“路径”（204A，204B）的高速缓冲存储器系统（200）。存储器系统包括功率控制器（244），功率控制器（244）根据包含正在进入存储器系统的每个输入地址（232）寻找的数据的方式选择性地向上和向下加电。

2. 发明申请

US20060171189A1 SRAM CELL USING TUNNEL CURRENT LOADING DEVICES 失效
标题翻译：使用隧道电流负载装置的SRAM单元
公开(公告)号：US20060171189A1
公开(公告)日：2006-08-03
申请号：US10906056
申请日：2005-02-01
申请人： Wagdi Abadeer , John Fifield , Harold Pilo
发明人： Wagdi Abadeer , John Fifield , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , G11C11/412
摘要： An SRAM cell with gate tunneling load devices. The SRAM cell uses PFET wordline transistors and NFET cross-coupled transistors. The PFET wordline transistors are fully conductive during read operations, thus a full voltage level is passed through the PFET to the high node of the cell from the bitline. Tunnel current load devices maintain the high node of the cell at full voltage level during standby state.
摘要翻译：具有栅极隧道负载装置的SRAM单元。 SRAM单元使用PFET字线晶体管和NFET交叉耦合晶体管。 PFET字线晶体管在读取操作期间是完全导电的，因此，整个电压电平从位线通过PFET到电池的高节点。隧道电流负载设备在待机状态下将电池的高节点保持在全电压电平。

3. 发明申请

US20070085557A1 METHOD AND APPARATUS FOR BURN-IN OPTIMIZATION 失效
标题翻译：用于烧结优化的方法和装置
公开(公告)号：US20070085557A1
公开(公告)日：2007-04-19
申请号：US11538833
申请日：2006-10-05
申请人： Wagdi Abadeer , Harold Pilo , Daryl Seitzer
发明人： Wagdi Abadeer , Harold Pilo , Daryl Seitzer
IPC分类号： G01R31/26
CPC分类号： G01R31/287 , G01R31/2874
摘要： The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.
摘要翻译：本发明提供一种用于优化集成电路的老化的方法和装置。该方法的一个实施例包括：执行集成电路的老化过程的第一部分; 在老化过程的第一部分期间监测集成电路的功耗; 增加老化温度，直到集成电路的功耗达到预定的最大功耗; 以及在增加的老化温度下执行集成电路的老化过程的后续部分。

4. 发明申请

US20060261835A1 METHOD AND APPARATUS FOR BURN-IN OPTIMIZATION 失效
标题翻译：用于烧结优化的方法和装置
公开(公告)号：US20060261835A1
公开(公告)日：2006-11-23
申请号：US10908620
申请日：2005-05-19
申请人： Wagdi Abadeer , Harold Pilo , Daryl Seitzer
发明人： Wagdi Abadeer , Harold Pilo , Daryl Seitzer
IPC分类号： G01R31/26
CPC分类号： G01R31/287 , G01R31/2874
摘要： The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.
摘要翻译：本发明提供一种用于优化集成电路的老化的方法和装置。该方法的一个实施例包括：执行集成电路的老化过程的第一部分; 在老化过程的第一部分期间监测集成电路的功耗; 增加老化温度，直到集成电路的功耗达到预定的最大功耗; 以及在增加的老化温度下执行集成电路的老化过程的后续部分。

5. 发明申请

US20060259840A1 SELF-TEST CIRCUITRY TO DETERMINE MINIMUM OPERATING VOLTAGE 审中-公开
标题翻译：自检电路确定最小工作电压
公开(公告)号：US20060259840A1
公开(公告)日：2006-11-16
申请号：US10908452
申请日：2005-05-12
申请人： Wagdi Abadeer , George Braceras , Anthony Bonaccio , Kevin Gorman
发明人： Wagdi Abadeer , George Braceras , Anthony Bonaccio , Kevin Gorman
IPC分类号： G01R31/28
CPC分类号： G01R31/3004
摘要： A solution for determining minimum operating voltages due to performance/power requirements would be valid for a wide range of actual uses. The solution includes a test flow methodology for dynamically reducing power consumption under applied conditions while maintaining application performance via a BIST circuit. There is additionally provided a test flow method for dynamically reducing power consumption to the lowest possible stand-by/very low power level under applied conditions that will still be sufficient to maintain data/state information. One possible application would be for controlling the voltage supply to a group of particular circuits on an ASIC (Application Specific Integrated Circuit). These circuits are grouped together in a voltage island where they would receive a voltage supply that can be different from the voltage supply other circuits on the same chip are receiving. The same solution could be applied to a portion of a microprocessor (the cache logic control, for example).
摘要翻译：用于确定由于性能/功率要求而导致的最小工作电压的解决方案对于广泛的实际应用是有效的。该解决方案包括测试流程方法，用于在应用条件下动态降低功耗，同时通过BIST电路保持应用性能。另外提供了一种测试流程方法，用于在仍然足以维护数据/状态信息的应用条件下将功耗动态地降低到最低可能待机/极低功率水平。一种可能的应用是用于控制对ASIC（专用集成电路）上的一组特定电路的电压供应。这些电路分组在一个电压岛中，在那里它们将接收可以与同一芯片正在接收的其它电路的电压供给不同的电压源。相同的解决方案可以应用于微处理器的一部分（例如，高速缓存逻辑控制）。

6. 发明申请

US20050133884A1 Electronically programmable antifuse and circuits made therewith 有权
标题翻译：电子可编程反熔丝和由其制成的电路
公开(公告)号：US20050133884A1
公开(公告)日：2005-06-23
申请号：US11051703
申请日：2005-02-04
申请人： John Fifield , Wagdi Abadeer , William Tonti
发明人： John Fifield , Wagdi Abadeer , William Tonti
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).
摘要翻译：一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

7. 发明申请

US20050122160A1 Method and circuit for compensating for tunneling current 失效
标题翻译：用于补偿隧道电流的方法和电路
公开(公告)号：US20050122160A1
公开(公告)日：2005-06-09
申请号：US10731298
申请日：2003-12-09
申请人： Wagdi Abadeer , Jennifer Appleyard , John Fifield , William Tonti
发明人： Wagdi Abadeer , Jennifer Appleyard , John Fifield , William Tonti
IPC分类号： G05F3/02 , G05F3/24
CPC分类号： G05F3/242
摘要： A method and circuit for tunneling leakage current compensation, the method including: forcing a current of known value through a tunneling current leakage monitor device to provide a voltage signal; and regulating an on-chip power supply of the integrated circuit chip based on the voltage signal.
摘要翻译：一种用于隧道泄漏电流补偿的方法和电路，所述方法包括：通过隧道电流泄漏监测装置强制已知值的电流以提供电压信号; 以及基于所述电压信号来调节所述集成电路芯片的片上电源。

8. 发明申请

US20070120221A1 Electronically Programmable Antifuse and Circuits Made Therewith 有权
标题翻译：电子可编程防腐和电路
公开(公告)号：US20070120221A1
公开(公告)日：2007-05-31
申请号：US11627723
申请日：2007-01-26
申请人： John Fifield , Wagdi Abadeer , William Tonti
发明人： John Fifield , Wagdi Abadeer , William Tonti
IPC分类号： H01L29/00 , H01L21/326
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).
摘要翻译：一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

9. 发明申请

US20060060938A1 Resettable fuse device and method of fabricating the same 有权
标题翻译：可复位保险丝装置及其制造方法
公开(公告)号：US20060060938A1
公开(公告)日：2006-03-23
申请号：US10948773
申请日：2004-09-23
申请人： Wagdi Abadeer , John Fifield , Robert Gauthier , William Tonti
发明人： Wagdi Abadeer , John Fifield , Robert Gauthier , William Tonti
IPC分类号： H01L29/00 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.
摘要翻译：在半导体衬底（10）的一个表面上制造可重置熔丝器件，并且包括：具有第一和第二端的栅极区域（20）源极节点（81），其形成在所述栅极区域的第一端附近; 形成为将源极节点连接到栅极区域的第一端的延伸区域（52）以及漏极节点（80），其形成在栅极区域的第二端附近，并且与栅极区分离距离（D），使得在向漏极节点施加预定的偏置电压时，漏极节点和栅极区域的第二端通过结损耗完成。栅极电介质（30）和栅电极（40）形成在栅极区域上方。当预定偏压施加到漏极节点和栅电极时，电流在源节点和漏极节点之间流动。

10. 发明申请

US20060091951A1 INTEGRATED CIRCUIT AMPLIFIER DEVICE AND METHOD USING FET TUNNELING GATE CURRENT 失效
标题翻译：集成电路放大器装置及使用FET隧道栅极电流的方法
公开(公告)号：US20060091951A1
公开(公告)日：2006-05-04
申请号：US10904238
申请日：2004-10-29
申请人： Wagdi Abadeer , Anthony Bonaccio , Kiran Chatty , John Fifield
发明人： Wagdi Abadeer , Anthony Bonaccio , Kiran Chatty , John Fifield
IPC分类号： H03F3/45 , H03F3/16
CPC分类号： H03F3/16 , H03F3/45179 , H03F3/505 , H03F2203/45468
摘要： An integrated circuit amplifier includes, in an exemplary embodiment, a first field effect transistor (FET) device configured as a source follower and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the source follower. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the source follower is configured so as to set an output conductance of the amplifier.
摘要翻译：在示例性实施例中，集成电路放大器包括被配置为源极跟随器的第一场效应晶体管（FET）器件和被配置为隧道栅极FET的第二FET器件，所述隧道栅极FET耦合到源极跟随器。隧道栅极FET进一步配置为设置放大器的跨导，并且配置源极跟随器以便设置放大器的输出电导。

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