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1. 发明授权

US06714113B1 Inductor for integrated circuits 有权
标题翻译：集成电路电感
公开(公告)号：US06714113B1
公开(公告)日：2004-03-30
申请号：US09712369
申请日：2000-11-14
申请人： Wagdi Abadeer , Robert A. Groves , Patrick Hansen
发明人： Wagdi Abadeer , Robert A. Groves , Patrick Hansen
IPC分类号： H01F2728
CPC分类号： H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An inductor is integrated in VLSI and ULSI technology products for very high frequency applications. The inductor is in a microstrip transmission line configuration which can be designed in a form of straight line, spiral line or Meander line. The inductor is formed by shorting the microstrip center conductor to the lower level ground plane at one end of the transmission line. This results in an inductance which, for a given design of transmission line, and in a specified frequency range, is independent of frequency, within the operating design range. The microstrip transmission line provides an inductance which could be used on any type of substrate, with either low or high resistivity. The microstrip transmission line could utilize two or all of the metal wiring levels of the technology, allowing a wide range of inductance and quality factor design tradeoffs. An important feature in this trade-off is the ability to utilize lower (below the inductor) metal wiring levels, as well as lower silicon and polysilicon areas for other than inductor design purposes, without affecting the operation of the inductor. This is because of the isolation properties of this inductor system. By utilizing isolation layers with low relative dielectric constant, Further enhancements of the system are achieved. The inductance of this system is constant within 10% over a frequency range extending from about 8 GHz to about 35 GHz This inductor system allows the design to be optimized, through several parameters, to achieve the desired performance.
摘要翻译：电感器集成在VLSI和ULSI技术产品中，适用于非常高频率的应用。电感器处于微带传输线配置中，可以以直线，螺旋线或曲折线的形式设计。电感器通过在传输线的一端将微带中心导体短路到下层接地平面而形成。这导致对于给定的传输线设计并且在指定的频率范围内，在操作设计范围内的电感是独立于频率的。微带传输线提供可用于任何类型的基板的电感，具有低或高电阻率。微带传输线可以利用该技术的两个或所有金属布线级别，允许广泛的电感和品质因数设计权衡。这种折衷的一个重要特征是能够利用低于（电感）以下的金属布线水平，以及除了电感器设计目的之外的较低的硅和多晶硅区域，而不会影响电感器的工作。这是因为这个电感系统的隔离性能。通过利用具有低相对介电常数的隔离层，实现了系统的进一步增强。该系统的电感在从大约8 GHz到大约35 GHz的频率范围内恒定在10％以内。该电感系统允许通过几个参数优化设计以实现所需的性能。

2. 发明申请

US20070252088A1 MONITORING IONIZING RADIATION IN SILICON-ON INSULATOR INTEGRATED CIRCUITS 有权
标题翻译：监测硅绝缘子集成电路中的离子化辐射
公开(公告)号：US20070252088A1
公开(公告)日：2007-11-01
申请号：US11380736
申请日：2006-04-28
申请人： Wagdi Abadeer , Ethan Cannon , Dennis Cox , William Tonti
发明人： Wagdi Abadeer , Ethan Cannon , Dennis Cox , William Tonti
IPC分类号： G01T1/02
CPC分类号： G01T1/244
摘要： A method, device and system for monitoring ionizing radiation. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.
摘要翻译：一种用于监测电离辐射的方法，装置和系统。该方法包括：收集由埋在硅衬底表面下方的氧化物层下面的硅层中形成的二极管的耗尽区收集的电离辐射感应电荷; 以及将二极管的阴极耦合到时钟逻辑电路的预充电节点，使得由二极管的耗尽区收集的电离辐射感应电荷将放电预充电节点并改变时钟逻辑电路的输出状态。

3. 发明申请

US20060249799A1 Concurrent fin-fet and thick body device fabrication 有权
公开(公告)号：US20060249799A1
公开(公告)日：2006-11-09
申请号：US11481120
申请日：2006-07-05
申请人： Wagdi Abadeer , Jeffrey Brown , David Fried , Robert Gauther , Edward Nowak , Jed Rankio , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , David Fried , Robert Gauther , Edward Nowak , Jed Rankio , William Tonti
IPC分类号： H01L29/76
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.

4. 发明申请

US20050133884A1 Electronically programmable antifuse and circuits made therewith 有权
标题翻译：电子可编程反熔丝和由其制成的电路
公开(公告)号：US20050133884A1
公开(公告)日：2005-06-23
申请号：US11051703
申请日：2005-02-04
申请人： John Fifield , Wagdi Abadeer , William Tonti
发明人： John Fifield , Wagdi Abadeer , William Tonti
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).
摘要翻译：一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

5. 发明申请

US20050122160A1 Method and circuit for compensating for tunneling current 失效
标题翻译：用于补偿隧道电流的方法和电路
公开(公告)号：US20050122160A1
公开(公告)日：2005-06-09
申请号：US10731298
申请日：2003-12-09
申请人： Wagdi Abadeer , Jennifer Appleyard , John Fifield , William Tonti
发明人： Wagdi Abadeer , Jennifer Appleyard , John Fifield , William Tonti
IPC分类号： G05F3/02 , G05F3/24
CPC分类号： G05F3/242
摘要： A method and circuit for tunneling leakage current compensation, the method including: forcing a current of known value through a tunneling current leakage monitor device to provide a voltage signal; and regulating an on-chip power supply of the integrated circuit chip based on the voltage signal.
摘要翻译：一种用于隧道泄漏电流补偿的方法和电路，所述方法包括：通过隧道电流泄漏监测装置强制已知值的电流以提供电压信号; 以及基于所述电压信号来调节所述集成电路芯片的片上电源。

6. 发明申请

US20070173029A1 Method for fabricating high performance metal-insulator-metal capacitor (MIMCAP) 审中-公开
标题翻译：制造高性能金属绝缘体金属电容器（MIMCAP）的方法
公开(公告)号：US20070173029A1
公开(公告)日：2007-07-26
申请号：US11340340
申请日：2006-01-26
申请人： Wagdi Abadeer , Jack Mandelman , Carl Radens , William Tonti
发明人： Wagdi Abadeer , Jack Mandelman , Carl Radens , William Tonti
IPC分类号： H01L21/20
CPC分类号： H01L28/60
摘要： A method of fabricating a high performance metal-insulator-metal capacitor (MIMCAP) includes providing a first inter-level dielectric (ILD) layer over an isolation region; forming a MIMCAP pattern in the first ILD layer over the isolation region; depositing a conformal conductive liner over the MIMCAP pattern and the first ILD layer; depositing an insulator over the conformal conductive liner; forming a contact pattern through the conformal conductive liner, the insulator and the first inter-level dielectric (ILD) layer; depositing a second conformal conductive liner over the MIMCAP pattern, the contact pattern and the first ILD layer; and depositing a conductive stud over the second conformal conductive liner in the MIMCAP pattern and the contact pattern. The method is applicable to both a conventional bulk semiconductor substrate and a silicon-on-insulator (SOI) substrate.
摘要翻译：一种制造高性能金属 - 绝缘体 - 金属电容器（MIMCAP）的方法包括在隔离区域上提供第一级间电介质层（ILD）层; 在隔离区域上的第一ILD层中形成MIMCAP图案; 在MIMCAP图案和第一ILD层上沉积共形导电衬垫; 在保形导电衬垫上沉积绝缘体; 通过所述共形导电衬垫，所述绝缘体和所述第一层间电介质层（ILD）层形成接触图案; 在MIMCAP图案，接触图案和第一ILD层上沉积第二共形导电衬垫; 以及在MIMCAP图案和接触图案中的第二共形导电衬垫上沉积导电柱。该方法适用于常规体半导体衬底和绝缘体上硅（SOI）衬底。

7. 发明申请

US20070170521A1 METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING 有权
公开(公告)号：US20070170521A1
公开(公告)日：2007-07-26
申请号：US11306827
申请日：2006-01-12
申请人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211
摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

8. 发明申请

US20070120221A1 Electronically Programmable Antifuse and Circuits Made Therewith 有权
标题翻译：电子可编程防腐和电路
公开(公告)号：US20070120221A1
公开(公告)日：2007-05-31
申请号：US11627723
申请日：2007-01-26
申请人： John Fifield , Wagdi Abadeer , William Tonti
发明人： John Fifield , Wagdi Abadeer , William Tonti
IPC分类号： H01L29/00 , H01L21/326
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).
摘要翻译：一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

9. 发明申请

US20060171189A1 SRAM CELL USING TUNNEL CURRENT LOADING DEVICES 失效
标题翻译：使用隧道电流负载装置的SRAM单元
公开(公告)号：US20060171189A1
公开(公告)日：2006-08-03
申请号：US10906056
申请日：2005-02-01
申请人： Wagdi Abadeer , John Fifield , Harold Pilo
发明人： Wagdi Abadeer , John Fifield , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , G11C11/412
摘要： An SRAM cell with gate tunneling load devices. The SRAM cell uses PFET wordline transistors and NFET cross-coupled transistors. The PFET wordline transistors are fully conductive during read operations, thus a full voltage level is passed through the PFET to the high node of the cell from the bitline. Tunnel current load devices maintain the high node of the cell at full voltage level during standby state.
摘要翻译：具有栅极隧道负载装置的SRAM单元。 SRAM单元使用PFET字线晶体管和NFET交叉耦合晶体管。 PFET字线晶体管在读取操作期间是完全导电的，因此，整个电压电平从位线通过PFET到电池的高节点。隧道电流负载设备在待机状态下将电池的高节点保持在全电压电平。

10. 发明申请

US20060060938A1 Resettable fuse device and method of fabricating the same 有权
标题翻译：可复位保险丝装置及其制造方法
公开(公告)号：US20060060938A1
公开(公告)日：2006-03-23
申请号：US10948773
申请日：2004-09-23
申请人： Wagdi Abadeer , John Fifield , Robert Gauthier , William Tonti
发明人： Wagdi Abadeer , John Fifield , Robert Gauthier , William Tonti
IPC分类号： H01L29/00 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.
摘要翻译：在半导体衬底（10）的一个表面上制造可重置熔丝器件，并且包括：具有第一和第二端的栅极区域（20）源极节点（81），其形成在所述栅极区域的第一端附近; 形成为将源极节点连接到栅极区域的第一端的延伸区域（52）以及漏极节点（80），其形成在栅极区域的第二端附近，并且与栅极区分离距离（D），使得在向漏极节点施加预定的偏置电压时，漏极节点和栅极区域的第二端通过结损耗完成。栅极电介质（30）和栅电极（40）形成在栅极区域上方。当预定偏压施加到漏极节点和栅电极时，电流在源节点和漏极节点之间流动。

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