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21. 发明申请

US20090295482A1 DRIVING AMPLIFIER CIRCUIT WITH DIGITAL CONTROL 有权
标题翻译：驱动放大器电路与数字控制
公开(公告)号：US20090295482A1
公开(公告)日：2009-12-03
申请号：US12131138
申请日：2008-06-02
申请人： Uday Dasgupta , Alexander Tanzil
发明人： Uday Dasgupta , Alexander Tanzil
IPC分类号： H03F3/26
CPC分类号： H03F3/303 , H03F3/45475 , H03F3/72 , H03F2203/45648 , H03F2203/45674 , H03F2203/45711 , H03F2203/45724 , H03F2203/7206
摘要： A driving amplifier circuit includes: a first driver for souring a load current to a load; a second driver for sinking the load current from the load; a first operational amplifier (op-amp) coupled to a differential input signal for driving the first driver; a second operational amplifier coupled to the differential input signal for driving the second driver; a first bias circuit for biasing the first driver; a second bias circuit for biasing the second driver; an enabling circuit, coupled to the first bias circuit and the second bias circuit, for enabling either the first bias circuit or the second bias circuit according to a control signal; and a digital control circuit, coupled to the enabling circuit, for monitoring currents of the first driver and the second driver to generate the control signal.
摘要翻译：驱动放大器电路包括：第一驱动器，用于向负载提供负载电流; 用于从负载中吸收负载电流的第二个驱动器; 耦合到用于驱动第一驱动器的差分输入信号的第一运算放大器（运算放大器）; 耦合到用于驱动第二驱动器的差分输入信号的第二运算放大器; 用于偏置第一驱动器的第一偏置电路; 用于偏置所述第二驱动器的第二偏置电路; 耦合到第一偏置电路和第二偏置电路的使能电路，用于根据控制信号实现第一偏置电路或第二偏置电路; 以及耦合到使能电路的数字控制电路，用于监视第一驱动器和第二驱动器的电流以产生控制信号。

22. 发明授权

US07592871B1 Fully differential current-feedback CMOS/bipolar operational amplifier 失效
标题翻译：全差分电流反馈CMOS /双极运算放大器
公开(公告)号：US07592871B1
公开(公告)日：2009-09-22
申请号：US12287964
申请日：2008-10-15
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F1/34 , H03F3/45183 , H03F3/45632 , H03F2200/513 , H03F2203/45366 , H03F2203/45431
摘要： A differential current amplifier circuit includes a first circuit generating a first pair of output currents based on a first input current to the differential current amplifier circuit. A second circuit generates a second pair of output currents based on a second input current to the differential current amplifier circuit. A first subtraction circuit generates a first output voltage based on a difference between one of the first pair of output currents and one of the second pair of output currents. A second subtraction circuit generates a second output voltage based on a difference between the other one of the second pair of output currents and the other one of the first pair of output currents.
摘要翻译：差分电流放大器电路包括基于对差分电流放大器电路的第一输入电流产生第一对输出电流的第一电路。第二电路基于到差分电流放大器电路的第二输入电流产生第二对输出电流。第一减法电路基于第一对输出电流中的一个与第二对输出电流中的一个之间的差产生第一输出电压。第二减法电路基于第二对输出电流中的另一个与第一对输出电流中的另一个之间的差产生第二输出电压。

23. 发明授权

US07215198B1 Fully differential current-feedback CMOS/bipolar operational amplifier 有权
标题翻译：全差分电流反馈CMOS /双极运算放大器
公开(公告)号：US07215198B1
公开(公告)日：2007-05-08
申请号：US10950201
申请日：2004-09-24
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F1/34 , H03F3/45183 , H03F3/45632 , H03F2200/513 , H03F2203/45366 , H03F2203/45431
摘要： A fully differential current feedback amplifier suitable for using in a fully differential operational amplifier circuit is disclosed. Symmetrical low input impedance input circuits receive a differential input current and provide a set of four currents that correspond to the differential input currents. These current are input to a pair of subtraction circuits that output a first voltage signal responsive to the positive difference and a second voltage signal responsive to the negative difference. In some embodiments these signals may be further amplified. A common mode circuit is provided that averages the output voltage and feeds back current in response to the subtraction circuits. In this way the average common mode output DC voltage can be set to particular voltage levels.
摘要翻译：公开了一种适用于全差分运算放大器电路中的全差分电流反馈放大器。对称低输入阻抗输入电路接收差分输入电流，并提供一组对应于差分输入电流的四个电流。这些电流被输入到一对减法电路，该对减法电路响应于正差异而输出第一电压信号，第二电压信号响应于负差值。在一些实施例中，这些信号可以被进一步放大。提供了一种共模电路，其对输出电压进行平均并响应减法电路反馈电流。以这种方式，平均共模输出直流电压可以设置为特定的电压电平。

24. 发明申请

US20050275466A1 Multi-gigabit/s transimpedance amplifier for optical networks 失效
标题翻译：用于光网络的多千兆位/秒跨阻放大器
公开(公告)号：US20050275466A1
公开(公告)日：2005-12-15
申请号：US10864950
申请日：2004-06-10
申请人： Uday Dasgupta , Chun Tan
发明人： Uday Dasgupta , Chun Tan
IPC分类号： H03F3/08
CPC分类号： H03F3/08
摘要： A Gigabit/s transimpedance amplifier system includes a forward-path amplifier section with a very large bandwidth and an overall frequency-selective feedback section which is active only from DC to low frequencies. The forward-path of the amplifier comprises a regulated cascode for receiving the input signal, a regulated cascode for receiving the feedback signal, a single-ended to differential converter and an output buffer. Stability and frequency selection is achieved by a bandwidth-limited operational amplifier in the feedback path. The Miller multiplication of a capacitive means in the operational amplifier creates a low-frequency pole and stabilizes the feedback loop and thereby limits the frequency range of the feedback.
摘要翻译：千兆/秒跨阻放大器系统包括具有非常大带宽的前向路径放大器部分和仅从DC到低频有效的总频率选择反馈部分。放大器的前向路径包括用于接收输入信号的调节共源共栅，用于接收反馈信号的调节共源共栅，单端到差分转换器和输出缓冲器。稳定性和频率选择由反馈路径中的带宽限制运算放大器实现。运算放大器中的电容装置的米勒乘法器产生低频极点并稳定反馈回路，从而限制反馈的频率范围。

25. 发明授权

US06839399B2 Programmable counter with half-integral steps 失效
标题翻译：可编程计数器，具有半积分步长
公开(公告)号：US06839399B2
公开(公告)日：2005-01-04
申请号：US10403446
申请日：2003-03-31
申请人： Chun Geik Tan , Uday Dasgupta
发明人： Chun Geik Tan , Uday Dasgupta
IPC分类号： H03K23/66 , H03K23/68 , H03K21/02
CPC分类号： H03K23/68 , H03K23/662
摘要： This invention provides a circuit and a method for programmable counters. It consists of a circuit and a method for unique programmable counters that provide half-integral as well as integral steps, such as 1.5, 2, 2.5, 3, 3.5, 4. This circuit and method are the first implementations of providing programmable counting with half-integral steps. The circuit and method of this invention can be extended via the cascading of toggle flip flops at the front end of the circuit of this invention. This provides the ability to enhance the speed of normal integral step counting applications. In addition, the cascading of the multiple copies of the circuit of this invention provides the ability to provide other fractional programmable counters. A key advantage of this invention is that the method of this invention is general enough to use any other type of counter sub-component beside the binary counter sub-component of this invention.

26. 发明授权

US06566961B2 Wide-band single-ended to differential converter in CMOS technology 有权
公开(公告)号：US06566961B2
公开(公告)日：2003-05-20
申请号：US09821511
申请日：2001-03-30
申请人： Uday Dasgupta , Teo Tian Hwee
发明人： Uday Dasgupta , Teo Tian Hwee
IPC分类号： H03F304
CPC分类号： H03F3/45183 , H03F2203/45508 , H03F2203/45544 , H03F2203/45562 , H03F2203/45631 , H03F2203/45702
摘要： A wide-band single-ended to differential converter (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively and using CMOS technology, is comprised of a first and a second stage. The very low amplitude and phase matching errors have been achieved firstly by the use of capacitive means CD across the gate and source of the first stage MOS transistor M1 with a value equal to the drain to ground (reference potential) parasitic capacitance of the tail current source device for the first stage, and secondly by using equal valued capacitive means CF1, CF2 in the second stage and setting their values to be several (5-10) times more than the gate-drain parasitic capacitances of either of the differential transistors of the second stage.

27. 发明授权

US06437612B1 Inductor-less RF/IF CMOS buffer for 50&OHgr; off-chip load driving 失效
标题翻译：无电感RF / IF CMOS缓冲器，用于50OMEGA片外负载驱动
公开(公告)号：US06437612B1
公开(公告)日：2002-08-20
申请号：US09996287
申请日：2001-11-28
申请人： Uday Dasgupta , Wooi Gan Teoh
发明人： Uday Dasgupta , Wooi Gan Teoh
IPC分类号： H03B100
CPC分类号： H03F1/308 , H03F1/301 , H03F2200/162
摘要： A buffer amplifier comprising a source follower-common drain circuit with a feedback path from the output of the drain follower to the input gate of the source follower. The feedback circuit is designed such that the output of the drain follower can be guaranteed to be at a voltage midway between the positive and the negative voltage supply of the circuit. This is the optimum operating point since it allows the largest signal swing. A small transconductance is realized by biasing the transistors of the feedback amplifier with very low currents; preferably by operating them in their weak inversion region. Feedback through the feedback amplifier is only present at DC (direct current) and at very low frequencies. This stabilizes the DC voltage at the drain of the common drain transistor, which, via an output capacitor, is also the output of the buffer amplifier.
摘要翻译：一种缓冲放大器，包括源极跟随器 - 公共漏极电路，其具有从漏极跟随器的输出端到源极跟随器的输入栅极的反馈路径。反馈电路被设计成使得能够保证漏极跟随器的输出处于电路的正电压和负电源之间的中间电压。这是最佳的操作点，因为它允许最大的信号摆幅。通过以非常低的电流偏置反馈放大器的晶体管来实现小跨导; 优选通过将它们操作在它们的弱反转区域中。通过反馈放大器的反馈仅存在于DC（直流）和非常低的频率下。这使得公共漏极晶体管的漏极处的直流电压稳定，其通过输出电容器也是缓冲放大器的输出。

28. 发明授权

US08427122B2 Enhancement of power supply rejection for operational amplifiers and voltage regulators 有权
标题翻译：增强运算放大器和稳压器的电源抑制
公开(公告)号：US08427122B2
公开(公告)日：2013-04-23
申请号：US12704506
申请日：2010-02-11
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： G05F1/565
CPC分类号： H02M1/15
摘要： A scheme for enhancement of the power-supply ripple rejection for operational amplifiers (op-amps) and low-dropout (LDO) voltage regulators is described. The scheme adds calculated amounts of current derived from the power-supply ripple with the input differential pair current to cancel off the output ripple, improving the high-frequency power-supply ripple rejection without requiring a substantial redesign of the circuitry involved.
摘要翻译：描述了增强运算放大器（运算放大器）和低压差（LDO）稳压器的电源纹波抑制的方案。该方案将计算出的电源纹波电流与输入差分对电流相加，以消除输出纹波，从而改善高频电源纹波抑制，而无需重新设计所涉及的电路。

29. 发明授权

US08073894B1 Compact switched-capacitor FIR filter implementation 有权
标题翻译：紧凑型开关电容FIR滤波器实现
公开(公告)号：US08073894B1
公开(公告)日：2011-12-06
申请号：US11935815
申请日：2007-11-06
申请人： Uday Dasgupta , Qing Chen
发明人： Uday Dasgupta , Qing Chen
IPC分类号： G06G7/02
CPC分类号： H03H15/00 , H03H19/004
摘要： A system is provided to perform non-recursive signal processing tasks using a sampled data technique and a network of switched-capacitor filters. The input analog signal is sampled in a time sequence manner at regular time intervals in order to obtain analog-valued samples. These samples are collected into data blocks and the data blocks are assembled into a set of data blocks. The successive data blocks belonging to a set of data blocks partially overlap with the first data block. The non-recursive signal processing is performed on all of the data blocks of the set substantially simultaneously, using a parallel network of switched capacitor filters, in order to produce a processed analog output signal. Each individual processing path of the parallel network of switched capacitor filters processes a specific data block of the set of data blocks. The number of parallel processing paths is the same as one plus the degree of the polynomial representing the desired or overall input/output equation characterizing the non-recursive signal processing. An implementing architecture can be simplified by factorizing the polynomial representing the input/output equation into smaller sized polynomial sub-tasks that can each be implemented by a sub-system of parallel network of switched capacitor filters of smaller complexity.
摘要翻译：提供了一种使用采样数据技术和开关电容滤波器网络执行非递归信号处理任务的系统。为了获得模拟值样本，输入模拟信号以时间顺序方式以规则的时间间隔进行采样。将这些样本收集到数据块中，并将数据块组装成一组数据块。属于一组数据块的连续数据块与第一数据块部分重叠。使用开关电容滤波器的并联网络，基本上同时对所述集合的所有数据块执行非递归信号处理，以便产生经处理的模拟输出信号。开关电容滤波器的并联网络的每个单独处理路径处理该组数据块的特定数据块。并行处理路径的数量与一个加上代表表征非递归信号处理的期望或总体输入/输出方程的多项式的程度相同。可以通过将表示输入/输出方程的多项式分解为更小尺寸的多项式子任务来简化实现架构，其可以分别由较小复杂度的开关电容器滤波器的并联网络的子系统来实现。

30. 发明授权

US07973605B2 Three-stage frequency-compensated operational amplifier for driving large capacitive loads 有权
标题翻译：用于驱动大容性负载的三级频率补偿运算放大器
公开(公告)号：US07973605B2
公开(公告)日：2011-07-05
申请号：US12486759
申请日：2009-06-18
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： H03F1/14
CPC分类号： H03F3/45192 , H03F1/086 , H03F2200/153 , H03F2200/45 , H03F2203/45632 , H03F2203/45674
摘要： A three-stage frequency-compensated operational amplifier includes a first-stage circuit, a second-stage circuit incorporated with a first compensation circuit, a third-stage circuit, and a second compensation circuit. The three-stage frequency-compensated operational amplifier functions as a two-stage operational amplifier at high frequencies, thereby capable of driving large capacitive loads with low power consumption.
摘要翻译：三级频率补偿运算放大器包括第一级电路，并入有第一补偿电路的第二级电路，第三级电路和第二补偿电路。三级频率补偿运算放大器在高频下用作两级运算放大器，从而能够以低功耗驱动大容量负载。

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